Integrated circuit with sequentially-coupled charge storage and associated techniques

Patent metadata

Field	Value
Publication number	US-12169142-B2
Application number	US-202318489841-A
Country	US
Kind code	B2
Filing date	Oct 18, 2023
Priority date	Oct 22, 2020
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

First claim

What is claimed is:

1. A method, comprising:
generating, in a photodetection region, in response to receiving incident photons, charge carriers; and
reading out charge carriers from a second charge storage region while a first charge storage region receives charge carriers from the photodetection region,
wherein the first charge storage region is electrically coupled to the photodetection region to receive charge carriers, and the second charge storage region is electrically coupled to the first charge storage region to receive charge carriers.

2. The method of claim 1 , wherein reading out charge carriers from the second charge storage region while the first charge storage region receives charge carriers comprises inducing a potential barrier between the first and second charge storage regions while the first charge storage region receives charge carriers from the photodetection region and the second charge storage region reads out charge carriers.

3. The method of claim 2 , further comprising:
receiving, at a first transfer gate positioned, at least in part, between the first and second charge storage regions, a first control signal,
wherein the first control signal causes the first transfer gate to control the potential barrier between the first and second charge storage regions while the first charge storage region receives charge carriers from the photodetection region and the second charge storage region reads out charge carriers.

4. The method of claim 3 , further comprising:
biasing, by the first transfer gate, to control the potential barrier between the first and second charge storage regions, a first charge transfer channel,
wherein the first charge transfer channel connects the first charge storage region to the second charge storage region.

5. The method of claim 4 , further comprising:
receiving, at a second transfer gate positioned, at least in part, between the photodetection region and the first charge storage region, a second control signal; and
biasing, by the second transfer gate, to control the potential barrier between the photodetection region and the first charge storage region, a second charge transfer channel,
wherein:
the second control signal causes the second transfer gate to control a potential barrier between the photodetection region and the first charge storage region while a drain region receives charge carriers from the photodetection region, and
the second charge transfer channel connects the photodetection region to the first charge storage region.

6. The method of claim 1 , further comprising:
receiving, at a first transfer gate positioned, at least in part, between the first charge storage region and an intermediate charge storage region, a first control signal;
biasing, by the first transfer gate, to control a potential barrier between the first and intermediate charge storage regions, a first charge transfer channel;
receiving, at a second transfer gate positioned, at least in part, between the intermediate and second charge storage regions, a second control signal; and
biasing, by the second transfer gate, to control a potential barrier between the intermediate and second charge storage regions, a second charge transfer channel,
wherein:
the intermediate charge storage region is electrically coupled between the first and second charge storage regions,
the first charge transfer channel connects the first charge storage region to the intermediate charge storage region,
wherein the second charge transfer channel connects the intermediate charge storage region to the second charge storage region,
the first control signal causes the first transfer gate to control the potential barrier between the first and intermediate charge storage regions while the first charge storage region receives charge carriers from the photodetection region and the intermediate and second charge storage regions read out charge carriers, and
the second control signal causes the second transfer gate to control the potential barrier between the intermediate and second charge storage regions while the intermediate charge storage region receives charge carriers from the photodetection region via the first charge storage region and the second charge storage region reads out charge carriers.

7. The method of claim 1 , wherein reading out charge carriers from the second charge storage region while the first charge storage region receives charge carriers from the photodetection region comprises transferring charge carriers from the second charge storage region to a readout region to be sampled.

8. An integrated circuit, comprising:
a photodetection region configured to generate charge carriers in response to receiving incident photons;
a first charge storage region electrically coupled to the photodetection region to receive charge carriers; and
a second charge storage region electrically coupled to the first charge storage region to receive charge carriers,
wherein the integrated circuit is configured to read out charge carriers from the second charge storage region while the first charge storage region receives charge carriers from the photodetection region.

9. The integrated circuit of claim 8 , wherein the integrated circuit is configured to induce a potential barrier between the first and second charge storage regions while the first charge storage region receives charge carriers from the photodetection region and the second charge storage region reads out charge carriers.

10. The integrated circuit of claim 9 , further comprising a first transfer gate positioned, at least in part, between the first and second charge storage regions and configured to receive a first control signal that causes the first transfer gate to control the potential barrier between the first and second charge storage regions while the first charge storage region receives charge carriers from the photodetection region and the second charge storage region reads out charge carriers.

11. The integrated circuit of claim 10 , further comprising:
a first charge transfer channel connecting the first charge storage region to the second charge storage region and configured to be biased by the first transfer gate to control the potential barrier between the first and second charge storage regions.

12. The integrated circuit of claim 11 , further comprising:
a drain region electrically coupled to the photodetection region to receive charge carriers from the photodetection region;
a second transfer gate positioned, at least in part, between the photodetection region and the first charge storage region and configured to receive a second control signal that causes the second transfer gate to control a potential barrier between the photodetection region and the first charge storage region while the drain region receives charge carriers from the photodetection region; and
a second charge transfer channel connecting the photodetection region to the first charge storage region and configured to be biased by the second transfer gate to control the potential barrier between the photodetection region and the first charge storage region.

13. The integrated circuit of claim 10 , further comprising:
an intermediate charge storage region electrically coupled between the first and second charge storage regions;
a first transfer gate positioned, at least in part, between the first and intermediate charge storage regions and configured to receive a first control signal that causes the first transfer gate to control a potential barrier between the first and intermediate charge storage regions while the first charge storage region receives charge carriers from the p

Assignees

• Quantum Si Inc

Inventors

• Webster Eric A G
• Rearick Todd
• Thurston Thomas Raymond

Classifications

• H10F39/152

  One-dimensional array CCD image sensors · CPC title

• H10F39/1515

  Optical shielding · CPC title

• H10F39/011

  Manufacture or treatment of image sensors covered by group H10F39/12 · CPC title

• G01J2001/446

  Photodiode · CPC title

• B01J2219/00689

  using computers · CPC title