Magnetoresistive stack/structure and methods therefor

Patent metadata

Field	Value
Publication number	US-12167702-B2
Application number	US-202318123729-A
Country	US
Kind code	B2
Filing date	Mar 20, 2023
Priority date	Jan 18, 2019
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

First claim

We claim:

1. A magnetoresistive device, comprising:
a magnetically fixed region;
a magnetically free region positioned above or below the magnetically fixed region;
an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material;
encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material;
a conductor in electrical contact with the magnetically free region, wherein the encapsulation layers are substantially vertical relative to a plane of the conductor;
a top electrode positioned above the magnetically fixed region, wherein the encapsulation layers are formed vertically over opposing ends of the top electrode; and
a diode positioned between the magnetically fixed region and the top electrode.

2. The magnetoresistive device of claim 1 , wherein the magnetically free region is positioned below the magnetically fixed region.

3. The magnetoresistive device of claim 1 , wherein the first dielectric material includes magnesium oxide (MgO).

4. The magnetoresistive device of claim 1 , wherein a width and a thickness of the magnetically free region are approximately the same.

5. The magnetoresistive device of claim 1 , wherein the magnetically free region is made of material having a large exchange stiffness constant.

6. The magnetoresistive device of claim 1 , wherein the encapsulation layers extend vertically beyond the side walls of the magnetically free region and cover at least a portion of side walls of the intermediate region.

7. The magnetoresistive device of claim 1 , wherein the magnetically free region and the encapsulation layers formed on opposing sidewalls of the magnetically free region are rounded or oval-shaped.

8. The magnetoresistive device of claim 1 , wherein an easy axis of magnetization of the magnetically free region is aligned with a longest dimension of the magnetically free region, wherein the magnetically free region and the encapsulation layers produce an interfacial magnetic anisotropy perpendicular to an interface between the magnetically free region and the encapsulation layers, and wherein the interfacial magnetic anisotropy and the easy axis of magnetization of the magnetically free region are approximately in a same direction.

9. A magnetoresistive memory, comprising:
a plurality of magnetoresistive devices, wherein each magnetoresistive device includes a magnetically fixed region, a magnetically free region, an intermediate region positioned between the magnetically fixed region and the magnetically free region, encapsulation layers formed on opposing side walls of the magnetically free region, and a top electrode positioned above the magnetically fixed region, wherein the intermediate region and each of the encapsulation layers include a same dielectric material; and
a first conductor extending adjacent each magnetoresistive device of the plurality of magnetoresistive devices,
wherein the first conductor is in electrical contact with the magnetically free region of each magnetoresistive device, and wherein the encapsulation layers extend past an interface of a magnetoresistive device and the first conductor.

10. The magnetoresistive memory of claim 9 , wherein the first conductor is made of spin Hall material.

11. The magnetoresistive memory of claim 9 , wherein a length of the magnetically free region is equal to or greater than a width of the first conductor.

12. The magnetoresistive memory of claim 9 , wherein a width of the first conductor is smaller than a sum of a length of the magnetically free region and a total thickness of the encapsulation layers.

13. The magnetoresistive memory of claim 9 , wherein the encapsulation layers extend vertically beyond the side walls of the magnetically free region and cover at least a portion of side walls of the intermediate region and at least a portion of side walls of the magnetically fixed region.

14. The magnetoresistive memory of claim 9 , wherein the dielectric material includes magnesium oxide (MgO).

15. A magnetoresistive memory, comprising:
a plurality of magnetoresistive devices, wherein each magnetoresistive device includes a magnetically fixed region, a magnetically free region, an intermediate region positioned between the magnetically fixed region and the magnetically free region, encapsulation layers formed on opposing side walls of the magnetically free region, and a diode positioned above the magnetically fixed region, wherein the intermediate region and each of the encapsulation layers include a same dielectric material; and
a first conductor extending adjacent each magnetoresistive device of the plurality of magnetoresistive devices,
wherein the first conductor is in electrical contact with the magnetically free region of each magnetoresistive device, wherein a constantly-regulated current flows through the first conductor for write operations.

16. The magnetoresistive memory of claim 15 , wherein the dielectric material is magnesium oxide (MgO).

17. The magnetoresistive memory of claim 15 , wherein a width and a thickness of the magnetically free region are approximately the same.

18. The magnetoresistive memory of claim 15 , wherein the magnetically free region is made of a material having a large exchange stiffness constant.

19. The magnetoresistive memory of claim 15 , wherein the encapsulation layers extend vertically beyond the side walls of the magnetically free region and cover at least a portion of side walls of the intermediate region and at least a portion of side walls of the magnetically fixed region.

20. The magnetoresistive memory of claim 15 , wherein a length of the magnetically free region is equal to or greater than a width of the first conductor.

Assignees

• Everspin Technologies Inc

Inventors

• Ikegawa Sumio
• Lee Han Kyu
• Aggarwal Sanjeev
• Sun Jijun
• Alam Syed M
• Andre Thomas

Classifications

• H10N52/01

  Manufacture or treatment · CPC title

• H10N52/00

  Hall-effect devices (integrated devices or assemblies of multiple devices H10N59/00) · CPC title

• H10N50/85

  Materials of the active region · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• H10N50/01

  Manufacture or treatment · CPC title