Spin orbit torque (SOT) magnetic memory cell and array

Patent metadata

Field	Value
Publication number	US-9830968-B2
Application number	US-201615266120-A
Country	US
Kind code	B2
Filing date	Sep 15, 2016
Priority date	Mar 16, 2016
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A magnetic memory according to an embodiment includes: at least one memory cell, the memory cell comprising: a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer; a diode including an anode and a cathode, one of the anode and the cathode being electrically connected to the first magnetic layer; and a transistor including third and fourth terminals and a control terminal, the third terminal being electrically connected to the first terminal.

First claim

The invention claimed is:

1. A magnetic memory comprising:
a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal;
a magnetoresistive element including: a first magnetic layer having a fixed magnetization; a second magnetic layer having a changeable magnetization and being disposed between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer;
a diode including a third terminal and a fourth terminal, the third terminal being electrically connected to the first magnetic layer;
a transistor including fifth and sixth terminals and a control terminal, the fifth terminal being electrically connected to the first terminal; and
a circuit electrically connected to the second terminal, the fourth terminal, the sixth terminal, and the control terminal,
wherein
when information is to be written into the second magnetic layer, the circuit switches on the transistor, applies a reverse bias to the diode, and supplies current between the second terminal and the sixth terminal, and
when information is to be read from the second magnetic layer, the circuit switches off the transistor, and supplies current between the second terminal and the fourth terminal.

2. The memory according to claim 1 , further comprising:
a first wiring electrically connected to the second terminal, and a second wiring electrically connected to the fourth terminal,
wherein a direction from a source toward a drain of the transistor intersects with respective directions in which the first wiring and the second wiring extend.

3. The memory according to claim 1 , wherein the diode is a schottky diode or an MIM diode, the MIM diode having two electrodes with different work functions.

4. The memory according to claim 1 , wherein the diode is a schottky diode having an uneven impurity concentration.

5. The magnetic memory according to claim 1 , wherein the transistor is a recessed transistor.

6. The magnetic memory according to claim 1 , further comprising:
a first wiring electrically connected to the second terminal, a second wiring electrically connected to the fourth terminal, a third wiring electrically connected to the sixth terminal, and a fourth wiring electrically connected to the control terminal,
wherein the first and third wirings extend in a first direction, and the second and fourth wirings extend in a second direction.

7. The magnetic memory according to claim 1 , further comprising:
a first wiring electrically connected to the second terminal, a second wiring electrically connected to the fourth terminal, a third wiring electrically connected to the sixth terminal, and a fourth wiring electrically connected to the control terminal,
wherein a direction in which the first wiring extends intersects with respective directions in which the second and fourth wirings extend, and a direction in which the third wiring intersects with respective directions in which the second and fourth wirings extend.

8. The magnetic memory according to claim 1 , wherein the circuit includes a first circuit electrically connected to the fourth terminal and the control terminal, and a second circuit electrically connected to the second terminal and the sixth terminal.

9. A magnetic memory comprising:
a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal;
a magnetoresistive element including: a first magnetic layer having a fixed magnetization; a second magnetic layer having a changeable magnetization and being disposed between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer;
a bidirectional diode including a third terminal and a fourth terminal, the third terminal being electrically connected to the first magnetic layer;
a transistor including fifth and sixth terminals and a control terminal, the fifth terminal being electrically connected to the first terminal; and
a circuit electrically connected to the second terminal, the fourth terminal, the sixth terminal, and the control terminal,
wherein
when information is to be written into the second magnetic layer, the circuit switches on the transistor, applies a voltage equal to or less than a threshold value to the bidirectional diode, and supplies current between the second terminal and the sixth terminal, and
when information is to be read from the second magnetic layer, the circuit switches off the transistor, and supplies current between the second terminal and the fourth terminal.

10. The memory according to claim 9 , further comprising:
a first wiring electrically connected to the second terminal and a second wiring electrically connected to the fourth terminal, wherein a direction from a source toward a drain of the transistor intersects with respective directions in which the first wiring and the second wiring extend.

11. The magnetic memory according to claim 9 , wherein the transistor is a recessed transistor.

12. The magnetic memory according to claim 9 , further comprising:
a first wiring electrically connected to the second terminal, a second wiring electrically connected to the fourth terminal, a third wiring electrically connected to the sixth terminal, and a fourth wiring electrically connected to the control terminal,
wherein the first and third wirings extend in a first direction, and the second and fourth wirings extend in a second direction.

13. The magnetic memory according to claim 9 , further comprising:
a first wiring electrically connected to the second terminal, a second wiring electrically connected to the fourth terminal, a third wiring electrically connected to the sixth terminal, and a fourth wiring electrically connected to the control terminal, wherein a direction in which the first wiring extends intersects with respective directions in which the second and fourth wirings extend, and a direction in which the third wiring intersects with respective directions in which the second and fourth wirings extend.

14. The magnetic memory according to claim 9 , wherein the circuit includes a first circuit electrically connected to the fourth terminal and the control terminal, and a second circuit electrically connected to the second terminal and the sixth terminal.

Assignees

• Toshiba Kk

Inventors

• Shimomura Naoharu
• Asao Yoshiaki
• Ishihara Takamitsu

Classifications

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/08

  Electricity · mapped topic

• H01L27/224

  Electricity · mapped topic

• G11C11/1675

  Writing or programming circuits or methods · CPC title