Partial speed changes to improve in-order transfer

Patent metadata

Field	Value
Publication number	US-12166505-B2
Application number	US-202318383813-A
Country	US
Kind code	B2
Filing date	Oct 25, 2023
Priority date	Sep 20, 2022
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A data storage device with partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory device will have at least one FMU that has a syndrome weight (SW). The disclosure proposes assigning FMU's based on the SW rate. At the time the command is read, the data storage device determines which level of decoder will be assigned to the FMU. The determination will then be checked according to different system environment parameters to maintain performance or reduce power consumption. The arrangement allows a more flexible system design that can adapt according to the current system status.

First claim

What is claimed is:

1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive a read request to retrieve a first data and a second data, wherein the first data is to be delivered to a host device prior to the second data;
determine that the first data will take longer to decode than the second data; and
adjust decoding speed of the second data such that the first data and the second data finish decoding substantially simultaneously.

2. The data storage device of claim 1 , wherein the controller comprises an error correction module, a host interface module (HIM), flash interface module (FIM), and volatile memory.

3. The data storage device of claim 1 , wherein the controller is further configured to detect a bit error rate (BER) for the first data and a BER for the second data.

4. The data storage device of claim 1 , wherein decoding speed of the first data is due to a higher BER than the second data.

5. The data storage device of claim 1 , wherein adjusting the decoding speed comprises reducing a clock frequency for a decoder that decodes the second data.

6. The data storage device of claim 5 , further comprising increasing a clock frequency for a decoder that decodes the first data.

7. The data storage device of claim 1 , wherein the first data and second data finish substantially simultaneously if the first data and the second data are finished within about 5% or less deviation.

8. The data storage device of claim 1 , wherein the controller is further configured to:
determine a syndrome weight for the first data and the second data;
assign the first data to a decoder, wherein the assigning the first data to a decoder is based on a calculated value;
assign the second data to a second decoder; and
reassign the first data and the second data to different decoders.

9. The data storage device of claim 1 , wherein the controller is further configured to:
adjust a clock frequency for at least one decoding unit while leaving at least one other decoding unit at an unchanged clock frequency, wherein the adjusting comprises reducing the clock frequency, and
deliver data decoded in the at least one other decoding unit to a host device prior to data decoded in the at least one decoding unit.

Assignees

• Western Digital Tech Inc
• Sandisk Technologies Inc

Inventors

• Benisty Shay
• Navon Ariel
• Bazarsky Alexander
• Avraham David

Classifications

• H03M13/015

  Simulation or testing of codes, e.g. bit error rate [BER] measurements · CPC title

• H03M13/1575

  Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• H03M13/1145 Primary

  Pipelined decoding at code word level, e.g. multiple code words being decoded simultaneously · CPC title

• H03M13/3707 Primary

  Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code · CPC title