Nonvolatile memory device and method of operating the same

Patent metadata

Field	Value
Publication number	US-9905301-B2
Application number	US-201615274071-A
Country	US
Kind code	B2
Filing date	Sep 23, 2016
Priority date	Nov 5, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A nonvolatile memory device includes a memory cell, a bit line, a page buffer, and a control logic. The page buffer is connected to the memory cell through the bit line and the page buffer is configured to precharge the bit line to perform a desired operation. The desired operation may be one of a read operation and a verify operation. The control logic is configured to control bit line development time differently according to a temperature after precharging the bit line during the desired operation. The control logic is configured to determine the bit line development time according to a period of a reference clock signal that includes a different frequency depending on the temperature and/or a temperature compensation pulse signal including a pulse width that varies based on the temperature.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory cell;
a bit line;
a page buffer connected to the memory cell through the bit line, the page buffer configured to precharge the bit line to perform a desired operation, wherein the desired operation is one of a read operation and a verify operation; and
control logic configured to control a bit line development time differently during the desired operation according to a temperature, wherein the bit line development time is after precharging the bit line during the desired operation,
the control logic configured to determine the bit line development time according to a period of a reference clock signal that includes a different frequency depending on the temperature.

2. The nonvolatile memory device of claim 1 , wherein
the control logic is configured to cut off a supply of a precharge voltage during the desired operation,
the control logic is configured to compare a voltage level of the bit line with a reference value after cutting off the supply of the precharge voltage, and
the bit line development time corresponds to an elapsed time after the control logic cuts off the supply of the precharge voltage until the control logic compares the voltage level of the bit line with the reference value.

3. The nonvolatile memory device of claim 1 , wherein
the control logic is configured to control the bit line development time to become shorter at a second temperature compared to the bit line development time at a first temperature if the second temperature is higher than the first temperature.

4. The nonvolatile memory device of claim 1 , wherein
the control logic is configured to generate the reference clock signal to have a higher frequency at a second temperature than at a first temperature if the second temperature is higher than the first temperature.

5. The nonvolatile memory device of claim 1 , wherein
the control logic includes a temperature voltage generator and a reference clock generator,
the temperature voltage generator is configured to generate a temperature voltage that varies depending on the temperature based on temperature information, and
the reference clock generator is configured to generate a reference clock signal that includes a different frequency depending on the temperature based on the temperature voltage.

6. The nonvolatile memory device of claim 5 , wherein
a second temperature is higher than a first temperature,
the temperature voltage generator is configured to generate the temperature voltage to have a lower level at the second temperature than at the first temperature, and
the reference clock generator is configured to generate the reference clock signal to have a higher frequency at the second temperature than at the first temperature.

7. A nonvolatile memory device comprising:
a memory cell;
a bit line;
a page buffer connected to the memory cell through the bit line, the page buffer configured to precharge the bit line to perform a desired operation, wherein the desired operation is one of a read operation and a verify operation; and
control logic configured to generate a temperature compensation pulse signal having a pulse width that varies based on a temperature,
the control logic configured to control a bit line development time differently based on the pulse width of the temperature compensation pulse signal, wherein the bit line development time is after precharging the bit line during the desired operation, wherein
the control logic includes a temperature voltage generator, a reference current generator, and a temperature compensation pulse generator,
the temperature voltage generator is configured to generate a temperature voltage that varies depending on the temperature based on temperature information,
the reference current generator is configured to provide a reference current to the temperature compensation pulse generator regardless of the temperature based on a first reference voltage, and
the temperature compensation pulse generator is configured to determine the pulse width of the temperature compensation pulse signal based on a voltage reduced from the temperature voltage at a specific rate according to the reference current and a second reference voltage.

8. The nonvolatile memory device of claim 7 , wherein the temperature compensation pulse generator is configured to determine the specific rate according to the reference current regardless of the temperature.

9. The nonvolatile memory device of claim 7 , wherein
a first temperature is less than a second temperature,
the temperature voltage generator is configured to generate the temperature voltage to have a lower level at the second temperature than at the first temperature, and
the temperature compensation pulse generator is configured to generate the temperature compensation pulse signal to have a large pulse width at the second temperature than at the first temperature.

10. The nonvolatile memory device of claim 7 , wherein the reference current generator includes:
a first resistor including one end connected to a ground terminal and an other end connected to a first node;
a second resistor including one end connected to the first node;
a first comparator configured to output a comparison result value based on the first reference voltage and a voltage of the first node;
a first transistor including one end connected to the other end of the second resistor, an other end of the first transistor being connected to a power supply terminal, the first transistor configured to turn on according to an output of the first comparator;
a second transistor including one end connected to the power supply terminal and an other end connected to a second node, and the second transistor configured to turn on according to the output of the first comparator; and
a third transistor including one end connected to the second node and an other end connected to the ground terminal, and the third transistor configured to turn on according to a voltage level of the second node.

11. The nonvolatile memory device of claim 10 , wherein the temperature compensation pulse generator includes:
a fourth transistor including one end connected to the ground terminal and an other end connected to a third node, the fourth transistor configured to turn on according to the voltage level of the second node;
a fifth transistor including one end connected to the third node and an other end connected to a fourth node;
a sixth transistor including one end connected to the fourth node and an other end of which is connected to a temperature voltage terminal;
a first capacitor connected between the fourth node and the ground terminal; and
a second comparator configured to generate the temperature compensation pulse signal based on the second reference voltage and a voltage of the fourth node,
wherein the fifth and sixth transistors are configured to complementarily turn on or turn off according to a start signal.

12. The nonvolatile memory device of claim 11 , wherein
the first capacitor is configured to charge based on the temperature voltage and is configured to discharge based on the reference current, and
the voltage of the fourth node is determined according to charge and discharge of the first capacitor.

13. The nonvolatile memory device of claim 11 , wherein the voltage of the fourth node is reduced from the temperature voltage according to a time constant of the first capacitor.

14. The nonvolatile memory device of claim 10 , wherein the reference current is determined according to the voltage level of the first node.

15.

Assignees

• Yoo Pil Seon
• Lee Ji Sang
• Choo Gyosoo
• Samsung Electronics Co Ltd

Inventors

• Yoo Pil Seon
• Lee Ji Sang
• Choo Gyosoo

Classifications

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/24 Primary

  Bit-line control circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title