Reactive power management for non-volatile memory controllers

Patent metadata

Field	Value
Publication number	US-10514748-B2
Application number	US-201715716961-A
Country	US
Kind code	B2
Filing date	Sep 27, 2017
Priority date	Sep 27, 2017
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

Systems, methods, and apparatus are provided that can reduce power consumption of memory controllers in response to memory command backlog in various situations. A data storage device includes a plurality of sets of non-volatile memory (NVM) devices, a central controller, and a plurality of channel controllers. Each channel controller is coupled to a distinct set of the plurality of sets of NVM devices. Each channel controller includes a command queue configured to store pending memory commands and provide backlog information. The central controller is configured to receive the backlog information of the command queues of the plurality of channel controllers, and adjust a clock frequency of the central controller and one or more clock frequencies of the plurality of channel controllers based on the backlog information such that the pending memory commands in each of the command queues are below a predetermined threshold level.

First claim

What is claimed is:

1. A data storage device comprising:
a plurality of sets of non-volatile memory (NVM) devices;
a central controller; and
a plurality of channel controllers, each channel controller coupled to a distinct set of the plurality of sets of NVM devices, each channel controller comprising a command queue configured to store pending memory commands and provide backlog information,
wherein the central controller is configured to:
receive the backlog information of the command queues of the plurality of channel controllers; and
adjust a clock frequency of the central controller and one or more clock frequencies of the plurality of channel controllers based on the backlog information such that the pending memory commands in each of the command queues are below a predetermined threshold level.

2. The data storage device of claim 1 , wherein the central controller is further configured to:
reduce the clock frequency of the central controller when the backlog information indicates that the pending memory commands in the command queue of at least one of the channel controllers exceeds a predetermined threshold level.

3. The data storage device of claim 1 , wherein the central controller is further configured to:
reduce at least one of the clock frequency of the central controller or the one or more clock frequencies of the plurality of channel controllers based on the backlog information.

4. The data storage device of claim 3 , wherein the central controller is further configured to:
reduce at least one of the clock frequency of the central controller or the one or more clock frequencies of the plurality of channel controllers when the backlog information indicates that a memory command processing throughput of the central controller is different from that of at least one of the channel controllers.

5. The data storage device of claim 3 , wherein each of the plurality of channel controllers is configured to:
maintain a clock frequency of a memory interface coupled between the plurality of channel controllers and the plurality of sets of NVM devices.

6. The data storage device of claim 3 , wherein the central controller is further configured to:
determine reclaimed power credits corresponding to power saved when reducing at least one of the clock frequency of the central controller or the one or more clock frequencies of the plurality of channel controllers; and
allocate the reclaimed power credits to one or more of the plurality of channel controllers for executing memory commands.

7. The data storage device of claim 1 , wherein each of the plurality of channel controllers is configured to:
determine the backlog information;
receive power credits allocated by the central controller, based at least in part on the backlog information; and
limit execution of memory commands in the command queue in accordance with the received power credits.

8. The data storage device of claim 7 , wherein each of the plurality of channel controllers is further configured to:
control a speed of issuance of the memory commands to the distinct set of the plurality of sets of NVM devices based on the power credits.

9. A method of operating a data storage device comprising a central controller and a plurality of channel controllers, the method comprising:
at the central controller, issuing memory commands to the plurality of channel controllers, each of the channel controllers comprising a command queue for storing the corresponding memory commands for a distinct set of a plurality of sets of non-volatile memory (NVM) devices and providing backlog information;
at the central controller, receiving the backlog information of the pending memory commands in the command queues; and
adjusting a clock frequency of the central controller and one or more clock frequencies of the plurality of channel controllers based on the backlog information such that the pending memory commands in each of the command queues are below a predetermined threshold level.

10. The method of claim 9 , further comprising:
reducing at least one of the clock frequency of the central controller or the one or more clock frequencies of the plurality of channel controllers based on the backlog information.

11. The method of claim 10 , further comprising:
reducing at least one of the clock frequency of the central controller or the one or more clock frequencies of the plurality of channel controllers when the backlog information indicates that a memory command processing throughput of the central controller is different from that of at least one of the channel controllers.

12. The method of claim 10 , further comprising, at each of the plurality of channel controllers:
maintaining a clock frequency of a memory interface coupled between the plurality of channel controllers and the plurality of sets of NVM devices.

13. The method of claim 10 , further comprising:
determining reclaimed power credits corresponding to power saved when reducing at least one of the clock frequency of the central controller or the one or more clock frequencies of the plurality of channel controllers; and
allocating the reclaimed power credits to one or more of the plurality of channel controllers for executing memory commands.

14. The method of claim 9 , further comprising, at each of the channel controllers:
determining the backlog information of the command queue;
receiving power credits allocated by the central controller, based at least in part on the backlog information; and
limit execution of memory commands in the command queue in accordance with the received power credits.

15. The method of claim 14 , further comprising, at each of the plurality of channel controllers:
controlling a speed of issuance of the memory commands to the distinct set of the plurality of sets of NVM devices based on the power credits.

Assignees

• Western Digital Tech Inc

Inventors

• Tidwell Reed P
• Weinberg Yoav
• Tuers Daniel
• Davidson Matthew
• Erez Eran

Classifications

• G06F3/0625 Primary

  Power saving in storage systems · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title