Providing a lower inductance path in a routing substrate for a capacitor, and related electronic devices and fabrication methods

Patent metadata

Field	Value
Publication number	US-12160952-B2
Application number	US-202217934651-A
Country	US
Kind code	B2
Filing date	Sep 23, 2022
Priority date	Sep 23, 2022
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

Electronic devices that include a routing substrate with lower inductance path for a capacitor, and related fabrication methods. In exemplary aspects, to provide lower interconnect inductance for a capacitor coupled to a power distribution network in the routing substrate, an additional metal layer that provides an additional, second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The additional, second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The disposing of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first and second power planes coupled to the capacitor as part of the power distribution network. This reduced dielectric thickness between first and second power planes coupled to the capacitor reduces the interconnect inductance for the capacitor.

First claim

What is claimed is:

1. An electronic device, comprising:
a routing substrate comprising a plurality of metallization layers parallel to each other in a first direction, the plurality of metallization layers comprising:
a first metallization layer, comprising:
a first metal layer comprising a first metal plane; and
a first dielectric layer adjacent to the first metal layer;

a second metallization layer adjacent to the first metallization layer, the second metallization layer comprising:
a second metal layer; and
a second dielectric layer adjacent to the second metal layer, the second dielectric layer between the first metal layer and the second metal layer in a second direction orthogonal to the first direction; and

a second metal plane disposed in the second dielectric layer, the second metal plane between the first metal layer and the second metal layer in the second direction; and

a capacitor coupled to the first metal plane and the second metal plane;
wherein:
the second metal plane is disposed a first distance from the first metal layer in the second direction;
the second metal plane is disposed a second distance in the second direction from the second metal layer; and
the first distance is less than the second distance.

2. The electronic device of claim 1 , wherein:
the first metal plane and the second metal layer are configured to create a first interconnect inductance in response to a voltage differential between the first metal plane and the second metal layer; and
the first metal plane and the second metal plane are configured to create a second interconnect inductance less than the first interconnect inductance, in response to the voltage differential between the first metal plane and the second metal plane.

3. The electronic device of claim 2 , wherein a ratio of the first interconnect inductance to the second interconnect inductance is at least 10.0.

4. The electronic device of claim 1 , wherein the second metal plane is coupled to a third metal plane in the second metal layer.

5. The electronic device of claim 4 , wherein:
the first metal plane is configured to be coupled to a first power signal of a power source to carry the first power signal; and
the second metal plane is configured to be coupled to a second power signal of the power source to carry the second power signal.

6. The electronic device of claim 1 , wherein:
the second dielectric layer has a first height in the second direction; and
the first distance is less than the first height.

7. The electronic device of claim 6 , wherein:
the first height is between fifty (50) micrometers (μm) and seventy (70) μm; and
the first distance is between 1.0 μm and 5.0 μm.

8. The electronic device of claim 6 , wherein a ratio between the first height and the first distance is at least 10.0.

9. The electronic device of claim 1 , wherein:
the second metal plane has a second height in the second direction; and
the second distance is less than the second height.

10. The electronic device of claim 9 , wherein:
the second height is between fifty (50) micrometers (μm) and seventy (70) μm; and
the second distance is between 1.0 μm and 5.0 μm.

11. The electronic device of claim 9 , wherein a ratio between the second height and the second distance is at least 10.0.

12. The electronic device of claim 1 , further comprising an integrated circuit (IC) package;
wherein:
the routing substrate comprises a circuit board;
the IC package is coupled to the circuit board; and
the IC package comprises a package substrate comprising a first metal line coupled to the first metal plane and a second metal line coupled to the second metal plane; and

further comprising a die coupled to the first metal line and the second metal line.

13. The electronic device of claim 12 , wherein:
the plurality of metallization layers are disposed in a first plane; and
the package substrate and the capacitor do not share a common second plane orthogonal to the first plane.

14. The electronic device of claim 1 , comprising an integrated circuit (IC) package, comprising:
a package substrate comprising the routing substrate; and
a die electrically coupled to the first metal plane and the second metal plane of the package substrate.

15. The electronic device of claim 14 , wherein:
the plurality of metallization layers are disposed in a first plane; and
the die and the capacitor do not share a common second plane orthogonal to the first plane.

16. The electronic device of claim 1 , wherein the capacitor comprises a deep trench capacitor (DTC).

17. The electronic device of claim 1 , wherein:
the plurality of metallization layers are disposed in a first plane; and
further comprising:
a second capacitor coupled to the routing substrate;
a die electrically coupled to the first metal plane and the second metal plane of the routing substrate; and
the die and the second capacitor share a common second plane orthogonal to the first plane.

18. The electronic device of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics systems; a drone; and a multicopter.

19. A method of fabricating an electronic device, comprising:
forming a routing substrate comprising a plurality of metallization layers parallel to each other in a first direction, comprising:
forming a first metallization layer, comprising:
forming a first metal layer comprising a first metal plane; and
forming a first dielectric layer adjacent to the first metal layer;

forming a second metallization layer, comprising:
forming a second metal layer; and
forming a second dielectric layer adjacent to the second metal layer, the second dielectric layer between the first metal layer and the second metal layer in a second direction orthogonal to the first direction;

forming a second metal plane in the second dielectric layer of the second metallization layer; and
coupling the second metallization layer to the first metallization layer such that the second metal plane is between the first metal layer and the second metal layer in the second direction; and

coupling a capacitor to the routing substrate, comprising:
coupling the capacitor to the first metal plane and the second metal plane;

wherein:
the second metal plane is disposed a first distance from the first metal layer in the second direction;
the second metal plane is disposed a second distance in the second direction from the second metal layer; and
the first distance is less than the second distance.

20. The method of claim 19 , further comprising coupling the second metal plane to a third metal plane in the second metal layer.

21. The method of claim 19 , wherein:
the second dielectric layer has a first height in the secon

Assignees

• Qualcomm Inc

Inventors

• Xie Biancun
• Pandey Shree Krishna
• Kim Chin-Kwan
• Lane Ryan
• Paynter Charles David

Classifications

• H05K2201/10734

  Ball grid array [BGA]; Bump grid array · CPC title

• H05K2201/10015

  Non-printed capacitor · CPC title

• H05K2201/09309

  Core having two or more power planes; Capacitive laminate of two power planes · CPC title

• H05K2201/093

  Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title