Electronic device, electronic apparatus, and method for supporting design of electronic device

Patent metadata

Field	Value
Publication number	US-11658106-B2
Application number	US-202117183405-A
Country	US
Kind code	B2
Filing date	Feb 24, 2021
Priority date	Sep 19, 2018
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

An electronic device includes: a board that includes an insulating film, a wiring layer and a via provided in the insulating film, and a plurality of power source pads and a plurality of ground pads which are provided in the insulating film so as to surround a capacitor region in which a capacitor is provided and to which a plurality of bumps is coupled; and an electronic component that is mounted at the board, and is electrically coupled to the plurality of power source pads and the plurality of ground pads through the wiring layer and the via. Further, a method for supporting design of the electronic device is provided.

First claim

What is claimed is:

1. An electronic device comprising:
a board that includes an insulating film, a wiring layer and a via provided in the insulating film, and a plurality of power source pads and a plurality of ground pads which are provided in the insulating film so as to surround a capacitor region in which a capacitor is provided and to which a plurality of bumps is coupled; and
an electronic component that is mounted at the board, and is electrically coupled to the plurality of power source pads and the plurality of ground pads through the wiring layer and the via,
at least one of
a case where the plurality of power source pads includes one or a plurality of first power source pads with which the via is in contact and one or a plurality of second power source pads with which the via is not in contact in a column lined up along a side of an outline of the capacitor region so as to be adjacent to the capacitor region and
a case where the plurality of ground pads includes one or a plurality of first ground pads with which the via is in contact and one or a plurality of second ground pads with which the via is not in contact in the column lined up along the side of the outline of the capacitor region so as to be adjacent to the capacitor region is satisfied,
the board includes the wiring layer electrically coupled to the one or plurality of second power source pads and the one or plurality of second ground pads in the capacitor region surrounded by the plurality of power source pads and the plurality of ground pads, and the wiring layer provided in the capacitor region is not in contact with the via in at least a partial region of regions adjacent to the column.

2. The electronic device according to claim 1 , wherein at least one of the one or plurality of second power source pads and the one or plurality of second ground pads is not in contact with the via.

3. The electronic device according to claim 1 , wherein at least one of the one or plurality of second power source pads and the one or plurality of second ground pads is arranged in a central portion of the side of the outline of the capacitor region, and is not arranged at ends of the side.

4. The electronic device according to claim 1 , wherein at least one of the one or plurality of second power source pads and the one or plurality of second ground pads is arranged from one end to the other end of the side of the outline of the capacitor region.

5. The electronic device according to claim 1 , wherein at least one of the one or plurality of second power source pads and the one or plurality of second ground pads is arranged so as to surround the capacitor region.

6. The electronic device according to claim 1 , wherein a length of the at least a partial region in a direction along the column is longer than lengths of one power source pad of the plurality of power source pads and one ground pad of the plurality of ground pads in the direction along the column.

7. The electronic device according to claim 1 , wherein a width of the at least a partial region in a direction intersecting the direction along the column is wider than 0 mm and equal to or narrower than 3.0 mm.

8. The electronic device according to claim 1 , wherein the at least a partial region is located so as to include a central portion of the side of the outline of the capacitor region.

9. An electronic apparatus comprising:
a first board;
a second board that includes an insulating film, a wiring layer and a via provided in the insulating film, and a plurality of power source pads and a plurality of ground pads provided in the insulating film so as to surround a capacitor region in which a capacitor is provided, and is mounted at the first board by a plurality of bumps being coupled to the plurality of power source pads and the plurality of ground pads; and
an electronic component that is mounted at the second board, and is electrically coupled to the plurality of power source pads and the plurality of ground pads through the wiring layer and the via,
wherein at least one of a case where the plurality of power source pads includes one or a plurality of first power source pads with which the via is in contact and one or a plurality of second power source pads with which the via is not in contact in a column lined up along a side of an outline of the capacitor region so as to be adjacent to the capacitor region and
a case where the plurality of ground pads includes one or a plurality of first ground pads with which the via is in contact and one or a plurality of second ground pads with which the via is not in contact in the column lined up along the side of the outline of the capacitor region so as to be adjacent to the capacitor region is satisfied,
the board includes the wiring layer electrically coupled to the one or plurality of second power source pads and the one or plurality of second ground pads in the capacitor region surrounded by the plurality of power source pads and the plurality of ground pads, and the wiring layer provided in the capacitor region is not in contact with the via in at least a partial region of regions adjacent to the column.

10. A method of supporting a design of an electronic device that includes a board, which includes an insulating film, a wiring layer and a via provided in the insulating film, and a plurality of power source pads and a plurality of ground pads which are provided in the insulating film so as to surround a capacitor region in which a capacitor is provided and to which a plurality of bumps is coupled, and an electronic component which is mounted at the board and is electrically coupled to the plurality of power source pads and the plurality of ground pads through the wiring layer and the via, the method comprising:
by using a computer, obtaining magnitudes of currents flowing through the plurality of bumps; and
correcting, when there is the bump of which the magnitude of the current exceeds a predetermined value among the plurality of bumps, design information of the board such that the magnitudes of the currents flowing through the plurality of bumps are in the predetermined value by decreasing a number of at least one of the power source pad and the ground pad to which the bump exceeding the predetermined value is coupled and which are in contact with the via among the plurality of power source pads and the plurality of ground pads,
the board includes the wiring layer electrically coupled to the one or plurality of second power source pads and the one or plurality of second ground pads in the capacitor region surrounded by the plurality of power source pads and the plurality of wound pads, and the wiring layer provided in the capacitor region is not in contact with the via in at least a partial region of regions adjacent to the column.

Assignees

• Fujitsu Ltd

Inventors

• Kawai Kenichi

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title