Atomic layer etch process using plasma in conjunction with a rapid thermal activation process

US12159789B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12159789-B2
Application numberUS-202117372847-A
CountryUS
Kind codeB2
Filing dateJul 12, 2021
Priority dateDec 14, 2016
Publication dateDec 3, 2024
Grant dateDec 3, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A process for etching a film layer on a semiconductor wafer is disclosed. The process is particularly well suited to etching carbon containing layers, such as hardmask layers, photoresist layers, and other low dielectric films. In accordance with the present disclosure, a reactive species generated from a plasma is contacted with a surface of the film layer. Simultaneously, the substrate or semiconductor wafer is subjected to rapid thermal heating cycles that increase the temperature past the activation temperature of the reaction in a controlled manner.

First claim

Opening claim text (preview).

What is claimed is: 1. A plasma reactor for processing one or more semiconductor wafers, the plasma reactor comprising: a plasma chamber, the plasma chamber comprising a dielectric sidewall and a ceiling, an induction coil disposed about the dielectric sidewall of the plasma chamber; an RF power generator coupled the induction coil through a matching network, the RF power generator operable to energize the induction coil with RF power to generate a substantially inductive plasma in the plasma chamber; a gas supply operable to provide a gas into the plasma chamber; a processing chamber separated from the plasma chamber by a separation grid, the separation grid operable to filter charged species generated in the substantially inductive plasma; a substrate holder disposed within the processing chamber; a plurality of lamps disposed at a location below the substrate holder; a window disposed between the plurality of lamps and the substrate holder; and a controller configured to control the plurality of lamps to implement a plurality of thermal heating cycles during an etch process, wherein each thermal cycle increases a temperature of the substrate above an activation temperature and decreases the temperature of the substrate below the activation temperature, wherein each thermal heating cycle comprises a pulse from a plurality of lamps, the pulse being less than 800 milliseconds. 2. The plasma reactor of claim 1 , further comprising a Faraday shield disposed between the induction coil and the dielectric sidewall. 3. The plasma reactor of claim 1 , wherein the substrate holder is operable to rotate a wafer. 4. The plasma reactor of claim 1 , wherein the dielectric sidewall comprises quartz. 5. The plasma reactor of claim 1 , wherein the window comprises a spectral filter. 6. The plasma reactor of claim 1 , wherein the plurality of lamps comprise a plurality of linear lamps. 7. The plasma reactor of claim 1 , further comprising a gas injection insert disposed in the plasma chamber. 8. The plasma reactor of claim 1 , wherein the controller is configured to adjust an amount of light provided by the plurality of lamps based at least in part on one or more temperature measurements of a wafer. 9. The plasma reactor of claim 1 , wherein the controller is configured to control the plurality of lamps to incrementally increase a temperature of a film layer on a wafer to control an etch rate during the etch process. 10. The plasma reactor of claim 9 , wherein the etch rate is an increasing and nonlinear etch rate during the etch process. 11. The plasma reactor of claim 9 , wherein the film layer is a doped amorphous carbon layer. 12. The plasma reactor of claim 11 , wherein the doped amorphous carbon layer is doped with boron. 13. A plasma reactor for processing one or more semiconductor wafer, the plasma reactor comprising: a plasma chamber, the plasma chamber comprising a dielectric sidewall and a ceiling, an induction coil disposed about the dielectric sidewall of the plasma chamber; an RF power generator coupled the induction coil through a matching network, the RF power generator operable to energize the induction coil with RF power to generate a substantially inductive plasma in the plasma chamber; a gas supply operable to provide a gas into the plasma chamber; a processing chamber separated from the plasma chamber by a separation grid, the separation grid operable to filter charged species generated in the substantially inductive plasma; a substrate holder disposed within the processing chamber; a plurality of lamps; and a controller configured to control the plurality of lamps to implement a plurality of thermal heating cycles during an etch process, each thermal heating cycle of the plurality of thermal heating cycles configured to incrementally increase a temperature of a film layer on a wafer to control an etch rate during the etch process, wherein each thermal cycle increases a temperature of the substrate above an activation temperature and decreases the temperature of the substrate below the activation temperature, wherein each thermal heating cycle comprises a pulse from the plurality of lamps, the pulse being less than 800 milliseconds. 14. The plasma reactor of claim 13 , wherein the controller is configured to adjust an amount of light provided by the plurality of lamps based at least in part on one or more temperature measurements of a wafer. 15. The plasma reactor of claim 13 , wherein the etch rate is an increasing and nonlinear etch rate during the etch process. 16. A plasma reactor for processing one or more semiconductor wafer, the plasma reactor comprising: a plasma chamber, the plasma chamber comprising a dielectric sidewall and a ceiling, an induction coil disposed about the dielectric sidewall of the plasma chamber; a Faraday shield disposed between the induction coil and the dielectric sidewall, an RF power generator coupled the induction coil through a matching network, the RF power generator operable to energize the induction coil with RF power to generate a substantially inductive plasma in the plasma chamber; a gas supply operable to provide a gas into the plasma chamber; a processing chamber separated from the plasma chamber by a separation grid, the separation grid operable to filter charged species generated in the substantially inductive plasma; a substrate holder disposed within the processing chamber; a plurality of linear lamps disposed at a location below the substrate holder; and a window disposed between the plurality of linear lamps and the substrate holder and a controller configured to control the plurality of linear lamps to incrementally increase a temperature of a doped amorphous carbon film layer on a wafer to control an etch rate during an etch process, wherein each thermal cycle increases a temperature of the substrate above an activation temperature and decreases the temperature of the substrate below the activation temperature, wherein each thermal heating cycle comprises a pulse from the plurality of lamps, the pulse being less than 800 milliseconds.

Assignees

Inventors

Classifications

  • Planarisation of organic insulating materials · CPC title

  • H10P50/287Primary

    by chemical means · CPC title

  • Maintaining constant desired temperature · CPC title

  • Gas control, e.g. control of the gas flow · CPC title

  • Temperature · CPC title

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What does patent US12159789B2 cover?
A process for etching a film layer on a semiconductor wafer is disclosed. The process is particularly well suited to etching carbon containing layers, such as hardmask layers, photoresist layers, and other low dielectric films. In accordance with the present disclosure, a reactive species generated from a plasma is contacted with a surface of the film layer. Simultaneously, the substrate or sem…
Who is the assignee on this patent?
Mattson Tech Inc, Beijing E Town Semiconductor Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P50/287. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 03 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).