Method for forming resistive random-access memory device

Patent metadata

Field	Value
Publication number	US-12156487-B2
Application number	US-202318382055-A
Country	US
Kind code	B2
Filing date	Oct 19, 2023
Priority date	Feb 1, 2021
Publication date	Nov 26, 2024
Grant date	Nov 26, 2024

Abstract

A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.

First claim

What is claimed is:

1. A method of forming a resistive random-access memory (RRAM) device, comprising:
sequentially depositing a bottom electrode layer and a dielectric hard mask layer on a first metal structure;
patterning the dielectric hard mask layer and the bottom electrode layer to form stack structures comprising bottom electrode lines and a dielectric layer;
forming an inter-dielectric layer on the first metal structure beside the bottom electrode lines, and a through hole being surrounded by the bottom electrode lines and the inter-dielectric layer; and
filling a resistive material conformally covering the through hole and a top electrode filling up the through hole, thereby the bottom electrode lines, the resistive material and the top electrode constituting a RRAM cell.

2. The method of forming a resistive random-access memory (RRAM) device according to claim 1 , further comprising:
depositing and patterning a cap layer on the first metal structure before the bottom electrode layer is deposited, so that the cap layer has openings for the bottom electrode lines physically connecting to the first metal structure.

3. The method of forming a resistive random-access memory (RRAM) device according to claim 2 , wherein the dielectric hard mask layer and the bottom electrode layer are patterned to form the stack structures directly on the openings of the cap layer and physically connecting to the first metal structure.

4. The method of forming a resistive random-access memory (RRAM) device according to claim 1 , wherein steps of forming the inter-dielectric layer comprise:
blanketly depositing a first dielectric layer on the first metal structure beside the bottom electrode lines after the dielectric hard mask layer and the bottom electrode layer are patterned;
planarizing the first dielectric layer to have a second dielectric layer having a flat top surface; and
removing a part of the second dielectric layer between the bottom electrode lines, and thereby the through hole surrounded by the bottom electrode lines and the inter-dielectric layer being formed.

5. The method of forming a resistive random-access memory (RRAM) device according to claim 1 , wherein steps of filling the resistive material conformally covering the through hole and the top electrode filling up the through hole comprise:
sequentially depositing a resistive material layer and a top electrode layer covering the through hole and the dielectric layer; and
removing the top electrode layer and the resistive material layer exceeding from the through hole.

6. The method of forming a resistive random-access memory (RRAM) device according to claim 1 , further comprising:
forming a via in the inter-dielectric layer beside the RRAM cell after the RRAM cell is formed, wherein the via contacts the first metal structure.

7. The method of forming a resistive random-access memory (RRAM) device according to claim 6 , further comprising:
forming a second metal structure directly contacting the resistive material, the top electrode and the via.

8. The method of forming a resistive random-access memory (RRAM) device according to claim 1 , wherein the resistive material has a U-shape cross-sectional profile.

9. The method of forming a resistive random-access memory (RRAM) device according to claim 1 , wherein the top electrode has an I-shape cross-sectional profile or a T-shape cross-sectional profile.

Assignees

• United Microelectronics Corp

Inventors

• Hsu Chia-Ching
• Xiang Wang
• Wang Shen-De

Classifications

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10N70/066

  by filling of openings, e.g. damascene method · CPC title

• H10N70/021

  Formation of switching materials, e.g. deposition of layers · CPC title

• H10B63/845

  the switching components being connected to a common vertical conductor · CPC title

• H10N70/841 Primary

  Electrodes · CPC title