Resistive memory and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9923028-B1
Application number	US-201715402630-A
Country	US
Kind code	B1
Filing date	Jan 10, 2017
Priority date	Dec 2, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate;
a plurality of first metal lines and a plurality of second metal lines disposed alternately in a plane that is horizontally positioned on the substrate;
an array of resistive random access memory (RRAM) elements disposed in the plane, wherein each of the RRAM elements is positioned between one of the first metal lines and one of the second metal lines that is adjacent to the one of the first metal lines, and the each of the RRAM elements comprises:
two barrier layers disposed on a sidewall of the one of the first metal lines and a sidewall of the one of the second metal lines, respectively; and
a resistance-variable layer disposed between the two barrier layers, wherein the barrier layers are more metal-rich than the resistance-variable layer;

a plurality of transistors, wherein source regions of the transistors are coupled to the first metal lines, respectively; and
a plurality of bit lines coupled to the second metal lines, respectively.

2. The semiconductor structure according to claim 1 , wherein the first metal lines and the second metal lines are disposed in parallel.

3. The semiconductor structure according to claim 1 , wherein the two barrier layers of the each of the RRAM elements comprise at least a material selected from the group consisting of: Al, Ti, Ta, Au, Ag, Pt, W, Ni, Ir, Cu, NiO x , Ta y O x , TiO x , HfO x , WO x , ZrO x , Al y O x , SrTiO x , Nb y O x and Y y O x .

4. The semiconductor structure according to claim 1 , wherein the resistance-variable layer of the each of the RRAM elements comprises at least a material selected from the group consisting of: NiO x , Ta y O x , TiO x , HfO x , WO x , ZrO x , Al y O x , SrTiO x , Nb y O x and Y y O x .

5. The semiconductor structure according to claim 1 , wherein the transistors are disposed on the substrate and at a level lower than the plane, and the bit lines are disposed at a level higher than the plane.

6. The semiconductor structure according to claim 1 , wherein the transistors are coupled to a plurality of word lines, respectively.

7. A semiconductor structure, comprising:
a memory unit structure, comprising:
a transistor;
a first electrode and two second electrodes disposed in a horizontal plane, wherein the first electrode is disposed between the two second electrodes, and the first electrode and the two second electrodes are disposed in parallel, and wherein the first electrode is coupled to a source region of the transistor; and
two resistive random access memory (RRAM) elements, wherein one of the two RRAM elements is disposed between the first electrode and one of the two second electrodes, and the other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes;

wherein the one of the two RRAM elements comprises:
two barrier layers disposed on a sidewall of the first electrode and a sidewall of the one of the two second electrodes, respectively; and
a resistance-variable layer disposed between the two barrier layers of the one of the two RRAM elements, wherein the barrier layers of the one of the two RRAM elements are more metal-rich than the resistance-variable layer of the one of the two RRAM elements; and

wherein the other one of the two RRAM elements comprises:
two barrier layers disposed on the other sidewall of the first electrode and a sidewall of the other one of the two second electrodes, respectively; and
a resistance-variable layer disposed between the two barrier layers of the other one of the two RRAM elements, wherein the barrier layers of the other one of the two RRAM elements are more metal-rich than the resistance-variable layer of the other one of the two RRAM elements.

8. The semiconductor structure according to claim 7 , wherein the memory unit structure comprises two RRAM cells coupled to the transistor, wherein one of the two RRAM cells comprises the first electrode, the one of the two second electrodes and the one of the two RRAM elements, and the other one of the two RRAM cells comprises the first electrode, the other one of the two second electrodes and the other one of the two RRAM elements.

9. The semiconductor structure according to claim 7 , wherein the two barrier layers of the one of the two RRAM elements and the two barrier layers of the other one of the two RRAM elements comprise at least a material selected from the group consisting of: Al, Ti, Ta, Au, Ag, Pt, W, Ni, Ir, Cu, NiO x , Ta y O x , TiO x , HfO x , WO x , ZrO x , Al y O x , SrTiO x , Nb y O x and Y y O x .

10. The semiconductor structure according to claim 7 , wherein the resistance-variable layer of the one of the two RRAM elements and the resistance-variable layer of the other one of the two RRAM elements comprise at least a material selected from the group consisting of: NiO x , Ta y O x , TiO x , HfO x , WO x , ZrO x , Al y O x , SrTiO x , Nb y O x and Y y O x .

Assignees

• United Microelectronics Corp

Inventors

• HSU Wen-Hsin
• Chen Ko-Chi
• Chang Tzu-Yun

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L45/146

  Electricity · mapped topic

• H01L45/08

  Electricity · mapped topic

• H01L45/147

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic