Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects

Patent metadata

Field	Value
Publication number	US-9564587-B1
Application number	US-201414588202-A
Country	US
Kind code	B1
Filing date	Dec 31, 2014
Priority date	Jun 30, 2011
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Providing for three-dimensional memory cells having enhanced electric field characteristics and/or memory cells located at broken interconnects is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance.

First claim

What is claimed is:

1. A method for fabricating memory with a segmented interconnect, comprising:
forming a stack of layers comprising a set of insulator layers comprising an electrical insulating material and a set of electrode layers comprising an electrical conducting metal, wherein insulator layers alternate with electrode layers in the stack of layers that are stacked in a first direction;
etching a via in the stack of layers comprising removing a portion of at least one electrode layer of the set of electrode layers, wherein the via segments the at least one electrode layer into a first portion and a second portion, exposing to the via a first surface of the first portion and a second surface of the second portion, and wherein at least one of the first surface or the second surface forms an oblique angle with respect to the first direction;
forming within the via, a second electrode layer differing from the set of electrode layers and comprising another electrical conducting metal; and
forming a switching layer between the second electrode layer and the first surface and between the second electrode layer and the second surface.

2. The method of claim 1 , further comprising etching a second via in the stack of layers comprising removing a second portion of the at least one electrode layer, wherein the second via segments the at least one electrode layer into the second portion and a third portion, exposing to the second via a third surface of the third portion and another second surface of the second portion, wherein the second portion represents a floating interconnect.

3. The method of claim 2 , further comprising forming within the second via another second electrode layer differing from the set of electrode layers and comprising the other electrical conducting metal.

4. The method of claim 3 , further comprising forming the switching layer between the other second electrode layer and the third surface and between the other second electrode layer and the other second surface.

5. The method of claim 4 , further comprising coupling a selection device to the second portion of the at least one electrode layer, wherein the selection device comprises a volatile memory cell.

6. The method of claim 1 , further comprising etching the via during formation of the stack of layers, wherein layers of the stack of layers are formed and subsequently patterned and etched in succession to form the via.

7. The method of claim 1 , further comprising forming a select layer between the at least one electrode layer and the switching layer.

8. The method of claim 7 , further comprising forming a conductive layer between the select layer and the switching layer.

9. The method of claim 1 , further comprising forming a barrier layer between the switching layer and the second electrode layer.

10. A memory device with a segmented interconnect, comprising:
a stack of layers comprising at least one insulator layer comprising an electrical insulating material in an alternating sequence with at least one electrode layer comprising an electrical conducting metal, wherein the stack of layers is arranged substantially along a first dimension normal to a surface plane of a substrate;
a via structure situated between a first segmented portion of the at least one electrode layer and a second segmented portion of the at least one electrode layer, comprising a resistive switching layer and a second electrode layer that differs from the at least one electrode layer: wherein the second segmented portion represents a floating interconnect; and
a memory cell formed at an intersection of the at least one electrode layer and the via structure, comprising a first electrode that corresponds to the at least one electrode layer, the resistive switching layer, and a second electrode that corresponds to the second electrode layer.

11. The memory device of claim 10 , wherein the intersection forms an oblique angle with respect to the first dimension.

12. The memory device of claim 10 , wherein the at least one electrode layer is at least one bitline of the memory device and the second electrode layer is a wordline of the memory device.

13. The memory device of claim 10 , wherein the at least one electrode layer is at least one wordline of the memory device and the second electrode layer is a bitline of the memory device.

14. The memory device of claim 10 , wherein the memory cell further comprising a select layer comprised of a metal oxide, TiO 2 , TiOx, Al 2 O 3 , AlOx, WO 3 , WOx, HfO 2 , HfOx, oxide, SiO 2 , SiOx, SiN, SiONx, poly Si, poly SiGe, doped polysilicon, doped poly SiGe, amorphous-poly Si, amorphous-poly SiGe, a non-linear element, or a diode.

15. The memory device of claim 14 , wherein the select layer is disposed between the resistive switching layer and the at least one electrode layer and has a thickness within a range of about 1 nanometers (nm) to about 50 nm.

16. The memory device of claim 14 , further comprising an electrical conductive layer disposed between the resistive switching layer and the select layer.

17. The memory device of claim 10 , further comprising a substrate disposed beneath the stack of layers, comprising a plurality of complementary metal oxide semiconductor (CMOS) devices.

18. The memory device of claim 10 , wherein the intersection is disposed at the first segmented portion of the at least one electrode layer.

19. The memory device of claim 18 , further comprising another memory cell at a second intersection between the second segmented portion of the at least one electrode layer and the via structure.

20. The memory device of claim 10 , wherein the memory cell is a non-volatile two-terminal memory cell.

21. A memory device with a floating interconnect, comprising:
a stack of layers comprising at least one insulator layer comprising an electrical insulating material in an alternating sequence with at least one electrode layer comprising an electrical conducting metal, wherein the stack of layers is arranged substantially along a first dimension normal to a surface plane of a substrate;
a first via structure situated between a first segmented portion of the at least one electrode layer and a second segmented portion of the at least one electrode layer, comprising a resistive switching layer and a second electrode layer that differs from the at least one electrode layer;
a second via structure situated between the second segmented portion and a third segmented portion of the at least one electrode layer comprising another resistive switching layer and another second electrode layer that differs from the at least one electrode layer, wherein the second segmented portion represents a floating electrode that is not coupled to an electrical source or an electrical ground; and
a memory cell formed at an intersection of the at least one electrode layer and the first via structure or the second via structure, comprising the resistive switching layer or the other resistive switching layer situated between a first electrode that corresponds to the at least one electrode layer and a second electrode that corresponds to the second electrode layer.

22. The memory device of claim 21 , wherein layers of the memory cell are arranged in sequence along a direction that forms an oblique angle with respect to the first dimension at least near the subset of the stack of layers.

23. The memory device of claim 21 , wherein the at least one electrode layer is at least one bitline of the

Assignees

• Crossbar Inc
• Crossbar Inc

Inventors

• Jo Sung Hyun
• Kim Kuk-Hwan
• Bettinger Joanna

Classifications

• H01L45/1608

  Electricity · mapped topic

• H01L45/146 Primary

  Electricity · mapped topic

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title