Substrate-less vertical diode integrated circuit structures

Patent metadata

Field	Value
Publication number	US-12154898-B2
Application number	US-202017133024-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Dec 23, 2020
Publication date	Nov 26, 2024
Grant date	Nov 26, 2024

Abstract

Substrate-less vertical diode integrated circuit structures, and methods of fabricating substrate-less vertical diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor fin in a dielectric layer, the semiconductor fin having a top and a bottom, and the dielectric layer having a top surface and a bottom surface. A first epitaxial semiconductor structure is on the top of the semiconductor fin. A second epitaxial semiconductor structure is on the bottom of the semiconductor fin. A first conductive contact is on the first epitaxial semiconductor structure. A second conductive contact is on the second epitaxial semiconductor structure.

First claim

What is claimed is:

1. A substrate-less integrated circuit structure, comprising:
a semiconductor fin in a dielectric layer, the semiconductor fin having a top and a bottom, and the dielectric layer having a top surface and a bottom surface;
a first epitaxial semiconductor structure on the top of the semiconductor fin;
a second epitaxial semiconductor structure on the bottom of the semiconductor fin;
a first conductive contact on the first epitaxial semiconductor structure; and
a second conductive contact on the second epitaxial semiconductor structure, wherein the second conductive contact has an uppermost surface above a bottommost surface of the second epitaxial semiconductor structure.

2. The substrate-less integrated circuit structure of claim 1 , wherein the first epitaxial semiconductor structure has a bottom below the top surface of the dielectric layer, and wherein the second epitaxial semiconductor structure has a top above the bottom surface of the dielectric layer.

3. The substrate-less integrated circuit structure of claim 1 , wherein the fin comprises silicon, and the first and second epitaxial semiconductor structures comprise silicon and germanium.

4. The substrate-less integrated circuit structure of claim 1 , wherein the first and second epitaxial semiconductor structures are faceted.

5. The substrate-less integrated circuit structure of claim 1 , wherein the integrated circuit structure is a vertical diode.

6. A computing device, comprising:
a board; and
a component coupled to the board, the component including a substrate-less integrated circuit structure, comprising:
a semiconductor fin in a dielectric layer, the semiconductor fin having a top and a bottom, and the dielectric layer having a top surface and a bottom surface;
a first epitaxial semiconductor structure on the top of the semiconductor fin;
a second epitaxial semiconductor structure on the bottom of the semiconductor fin;
a first conductive contact on the first epitaxial semiconductor structure; and
a second conductive contact on the second epitaxial semiconductor structure, wherein the second conductive contact has an uppermost surface above a bottommost surface of the second epitaxial semiconductor structure.

7. The computing device of claim 6 , further comprising:
a memory coupled to the board.

8. The computing device of claim 6 , further comprising:
a communication chip coupled to the board.

9. The computing device of claim 6 , wherein the component is a packaged integrated circuit die.

10. The computing device of claim 6 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

11. A substrate-less integrated circuit structure, comprising:
a plurality of fins in a dielectric layer;
a plurality of N-type epitaxial structures on a top of the plurality of fins;
a plurality of P-type epitaxial structures on a bottom of the plurality of fins;
a first conductive contact on the plurality of N-type epitaxial structures; and
a second conductive contact on the plurality of P-type epitaxial structures, wherein the second conductive contact has an uppermost surface above a bottommost surface of the plurality of P-type epitaxial structures.

12. The substrate-less integrated circuit structure of claim 11 , wherein the plurality of fins is a plurality of N-type fins.

13. The substrate-less integrated circuit structure of claim 11 , wherein the plurality of fins is a plurality of P-type fins.

14. The substrate-less integrated circuit structure of claim 11 , wherein the plurality of fins comprises silicon, the plurality of N-type epitaxial structures comprises silicon and germanium, and the plurality of P-type epitaxial structures comprises silicon and germanium.

15. The substrate-less integrated circuit structure of claim 11 , wherein the integrated circuit structure is a vertical diode.

16. A computing device, comprising:
a board; and
a component coupled to the board, the component including a substrate-less integrated circuit structure, comprising:
a plurality of fins in a dielectric layer;
a plurality of N-type epitaxial structures on a top of the plurality of fins;
a plurality of P-type epitaxial structures on a bottom of the plurality of fins;
a first conductive contact on the plurality of N-type epitaxial structures; and
a second conductive contact on the plurality of P-type epitaxial structures, wherein the second conductive contact has an uppermost surface above a bottommost surface of the plurality of P-type epitaxial structures.

17. The computing device of claim 16 , further comprising:
a memory coupled to the board.

18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.

19. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

20. The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Jayanthinarasimham Avyaya
• Greene Brian
• Vishwanath Suresh

Classifications

• H10P95/11

  Separation of active layers from substrates · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D8/00 Primary

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title