Replacement metal gate process for vertical transport field-effect transistor with self-aligned shared contacts

Patent metadata

Field	Value
Publication number	US-11271106-B2
Application number	US-202016813105-A
Country	US
Kind code	B2
Filing date	Mar 9, 2020
Priority date	Aug 21, 2018
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
forming a bottom source/drain region over a top surface of a substrate;
forming a plurality of fins over a top surface of the bottom source/drain region, the fins providing vertical transport channels for one or more vertical transport field-effect transistors; and
forming at least one self-aligned shared contact between an adjacent pair of the plurality of fins, the adjacent pair of the plurality of fins comprising a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor;
wherein the first vertical transport field-effect transistor comprises an n-type vertical transport field-effect transistor and the second vertical transport field-effect transistor comprises a p-type vertical transport field-effect transistor, and wherein the at least one self-aligned shared contact comprises a gate contact to a first gate conductor surrounding the first fin of the first vertical transport field-effect transistor and a second gate conductor surrounding the second fin of the second vertical transport field-effect transistor.

2. The method of claim 1 , further comprising forming at least one additional self-aligned shared contact disposed between an additional adjacent pair of the plurality of fins, the additional adjacent pair of the plurality of fins comprising a third fin providing a third vertical transport channel for a third vertical transport field-effect transistor and a fourth fin providing a second vertical transport channel for a fourth vertical transport-field effect transistor, wherein the third vertical transport field-effect transistor and the fourth vertical transport field-effect transistor comprise one of n-type and p-type vertical transport field-effect transistors, and wherein the at least one additional self-aligned shared contact comprises a contact to a portion of the bottom source/drain region shared by the third vertical transport field-effect transistor and the fourth vertical transport field-effect transistor.

3. The method of claim 2 , wherein the third vertical transport field-effect transistor is the same as one of the first vertical transport field-effect transistor and the second vertical transport field-effect transistor.

4. The method of claim 1 , further comprising forming at least one additional self-aligned shared contact disposed between an additional adjacent pair of the plurality of fins, the additional adjacent pair of the plurality of fins comprising a third fin providing a third vertical transport channel for a third vertical transport field-effect transistor and a fourth fin providing a second vertical transport channel for a fourth vertical transport-field effect transistor, wherein the third vertical transport field-effect transistor and the fourth vertical transport field-effect transistor comprise one of n-type and p-type vertical transport field-effect transistors, and wherein the at least one additional self-aligned shared contact comprises a contact to a portion of the bottom source/drain region shared by the third vertical transport field-effect transistor and the fourth vertical transport field-effect transistor.

5. The method of claim 4 , wherein the third vertical transport field-effect transistor is the same as one of the first vertical transport field-effect transistor and the second vertical transport field-effect transistor.

6. The method of claim 1 , further comprising:
forming a bottom spacer over the bottom source/drain region surrounding a portion of sidewalls of the plurality of fins;
forming a gate dielectric over the bottom spacer and surrounding a portion of the sidewalls of the plurality of fins; and
forming top source/drain regions disposed over top surfaces of the plurality of fins.

7. The method of claim 6 , further comprising forming a first gate conductor disposed over the gate dielectric surrounding ones of the plurality of fins providing vertical transport channels for n-type vertical transport field-effect transistors.

8. The method of claim 7 , further comprising forming a second gate conductor disposed over the gate dielectric surrounding ones of the plurality of fins providing vertical transport channels for p-type vertical transport field-effect transistors.

9. The method of claim 8 , further comprising forming self-aligned spacers disposed over the gate dielectric, the first gate conductor and the second gate conductor surrounding a portion of the sidewalls of the plurality of fins and sidewalls of the top source/drain regions.

10. The method of claim 9 , wherein the plurality of fins comprise at least a first pair of adjacent fins providing respective vertical transport channels for a first pair of vertical transport field-effect transistors, the first pair of vertical transport field-effect transistors comprising one of n-type vertical transport field-effect transistors and p-type vertical transport field-effect transistors.

11. A method of forming a semiconductor structure, comprising:
forming a bottom source/drain region over a top surface of a substrate;
forming a plurality of fins over a top surface of the bottom source/drain region, the fins providing vertical transport channels for one or more vertical transport field-effect transistors; and
forming at least one self-aligned shared contact between an adjacent pair of the plurality of fins, the adjacent pair of the plurality of fins comprising a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor;
forming a bottom spacer over the bottom source/drain region surrounding a portion of sidewalls of the plurality of fins;
forming a gate dielectric over the bottom spacer and surrounding a portion of the sidewalls of the plurality of fins;
forming top source/drain regions disposed over top surfaces of the plurality of fins;
forming a first gate conductor disposed over the gate dielectric surrounding ones of the plurality of fins providing vertical transport channels for n-type vertical transport field-effect transistors;
forming a second gate conductor disposed over the gate dielectric surrounding ones of the plurality of fins providing vertical transport channels for p-type vertical transport field-effect transistors;
forming self-aligned spacers disposed over the gate dielectric, the first gate conductor and the second gate conductor surrounding a portion of the sidewalls of the plurality of fins and sidewalls of the top source/drain regions;
wherein the plurality of fins comprise at least a first pair of adjacent fins providing respective vertical transport channels for a first pair of vertical transport field-effect transistors, the first pair of vertical transport field-effect transistors comprising one of n-type vertical transport field-effect transistors and p-type vertical transport field-effect transistors; and
forming inner spacers on sidewalls of the gate dielectric, one of the first gate conductor and the second gate conductor, and the self-aligned spacers between the first pair of adjacent fins.

12. The method of claim 11 , further comprising forming a first contact to the bottom source/drain region between the inner spacers between the first pair of adjacent fins, the first contact being shared by the first pair of vertical transport field-effect transistors.

13. A method of forming a semiconductor s

Assignees

• IBM

Inventors

• Bao Ruqiang
• Anderson Brent A
• Lee Choonghyun
• Jagannathan Hemanth

Classifications

• H10D84/837

  comprising vertical IGFETs · CPC title

• H10D84/83135

  the IGFETs characterised by having different gate conductor materials or different gate conductor implants · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/0195 Primary

  the components including vertical IGFETs · CPC title