Flip flop and design method for integrated circuit including same

Patent metadata

Field	Value
Publication number	US-12149249-B2
Application number	US-202318352171-A
Country	US
Kind code	B2
Filing date	Jul 13, 2023
Priority date	Apr 8, 2021
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A flip-flop includes a first master latch in a first row, a second master latch in a second row, a first slave latch in the first row, and a second slave latch in the second row. The first master latch and the second master latch are adjacently disposed in the second direction, and the first slave latch and the second slave latch are adjacently disposed in the second direction.

First claim

What is claimed is:

1. A flip-flop disposed in an integrated circuit (IC) layout, the IC circuit layout including alternating power lines defining rows of the IC circuit layout there between, the rows each extending lengthwise in a first direction, the flip-flop comprising:
a first sub-master latch disposed in one of a first row and an adjacent second row among the rows of the IC circuit layout, and configured to generate a signal at a first node in response to a first data signal, a clock signal, and a signal at a second node;
a second sub-master latch disposed in the other one of the first row and the second row in which the first sub-master latch is not disposed, wherein the second sub-master latch is configured to generate a signal at the second node in response to an inverted first data signal, the clock signal, and the signal at the first node;
a first sub-slave latch disposed in one of the first row and the second row, and configured to generate a signal at a third node in response to the clock signal, the signal at the first node, and a signal at a fourth node;
a second sub-slave latch disposed in the other one of the first row and the second row in which the first sub-slave latch is not disposed, wherein the second sub-slave latch is configured to generate the signal at the fourth node in response to the clock signal, the signal at the second node, and the signal at the third node,
a third sub-master latch disposed in one of a third row adjacent to the second row and a fourth row adjacent to the third row, and configured to generate a signal at a fifth node in response to a second data signal, the clock signal, and a signal at a sixth node;
a fourth sub-master latch disposed in the other one of the third row and the fourth row in which the third sub-master latch is not disposed, wherein the fourth sub-master latch is configured to generate the signal at the sixth node in response to an inverted second data signal, the clock signal, and the signal at the fifth node;
a third sub-slave latch disposed in one of the third row and the fourth row, and configured to generate a signal at a seventh node in response to the clock signal, the signal at the fifth node, and a signal at an eighth node; and
a fourth sub-slave latch disposed in the other one of the third row and the fourth row in which the third sub-slave latch is not disposed, wherein the fourth sub-slave latch is configured to generate the signal at the eighth node in response to the clock signal, the signal at the sixth node, and the signal at the seventh node,
wherein the first sub-master latch and the second sub-master latch are adjacently disposed in a second direction in different ones of the first and second rows, the second direction perpendicular to the first direction,
the first sub-slave latch and the second sub-slave latch are adjacently disposed in the second direction in different ones of the first and second rows,
the third sub-master latch and the fourth sub-master latch are adjacently disposed in the second direction in different ones of the third and fourth rows, and
the fourth sub-slave latch and the third sub-slave latch are adjacently disposed in the second direction in different ones of the third and fourth rows.

2. The flip-flop of claim 1 , further comprising:
a first gate electrode extending in the second direction across the first row and the second row and configured to commonly transmit the clock signal to the first sub-master latch and the second sub-master latch,
a second gate electrode extending in the second direction across the third row and the fourth row and configured to commonly transmit the clock signal to the third sub-master latch and the fourth sub-master latch.

3. The flip-flop of claim 1 , further comprising:
a first wiring line disposed in the first row, extending in the first direction, and transmitting the signal at the first node to the first sub-slave latch;
a second wiring line disposed in the second row, extending in the first direction, and transmitting the signal at the second node to the second sub-slave latch;
a third wiring line disposed in the third row, extending in the first direction, and transmitting the signal at the fifth node to the third sub-slave latch; and
a fourth wiring line disposed in the fourth row, extending in the first direction, and transmitting the signal at the sixth node to the fourth sub-slave latch.

4. The flip-flop of claim 3 , further comprising:
a fifth wiring line extending in the second direction across the first row and the second row and connected to the first wiring line to transmit the signal at the first node to the second sub-master latch;
a sixth wiring line extending in the second direction across the first row and the second row and connected to the second wiring line to transmit the signal at the second node to the first sub-master latch;
a seventh wiring line extending in the second direction across the third row and the fourth row and connected to the third wiring line to transmit the signal at the fifth node to the fourth sub-master latch; and
an eighth wiring line extending in the second direction across the third row and the fourth row and connected to the fourth wiring line to transmit the signal at the sixth node to the third sub-master latch.

5. The flip-flop of claim 1 , further comprising:
a third gate electrode extending in the second direction across the first row and the second row and configured to commonly transmit the clock signal to the first sub-slave latch and the second sub-slave latch; and
a fourth gate electrode extending in the second direction across the third row and the fourth row and configured to commonly transmit the clock signal to the third sub-slave latch and the fourth sub-slave latch.

6. The flip-flop of claim 5 , further comprising:
a ninth wiring line extending in the second direction across the first row and the second row and configured to transmit the signal at the third node to the second sub-slave latch;
a tenth wiring line extending in the second direction across the first row and the second row and configured to transmit the signal at the fourth node to the first sub-slave latch;
an eleventh wiring line extending in the second direction across the third row and the fourth row and configured to transmit the signal at the seventh node to the fourth sub-slave latch; and
a twelfth wiring line extending in the second direction across the third row and the fourth row and configured to transmit the signal at the eighth node to the third sub-slave latch.

7. The flip-flop of claim 1 , further comprising:
a first input inverter disposed in the first row, and configured to receive the first data signal and invert the first data signal;
a first output inverter disposed in the second row and configured to invert the signal at the fourth node;
a second input inverter disposed in the third row, and configured to receive the second data signal and invert the second data signal; and
a second output inverter disposed in the fourth row and configured to invert the signal at the eighth node.

8. The flip-flop of claim 1 , wherein the power lines each extend in the first direction, and are respectively disposed at a boundary between adjacent rows, and
wherein the power lines defining the first and second rows are configured to supply power to transistors included in at least one of the first sub-master latch, the second sub-master latch, the first sub-slave latch, and the second sub-slave latch, and
the power lines defining the third and fourth rows are configured to supply power to transistors included in at least one of the third sub-master latch, the fourth sub-master latch, the third sub-slave latch, and the fourth sub-slave latch.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Ahreum
• Lee Youngo
• Kim Minsu
• Choi Eunhee

Classifications

• H10D84/907

  CMOS gate arrays · CPC title

• H10D84/975

  Wiring regions or routing · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H03K19/094

  using field-effect transistors · CPC title

• H03K3/02332

  of the primary-secondary type · CPC title