Apparatus and method for low power fully-interruptible latches and master-slave flip-flops

Patent metadata

Field	Value
Publication number	US-9397641-B2
Application number	US-201514711686-A
Country	US
Kind code	B2
Filing date	May 13, 2015
Priority date	Oct 31, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

First claim

We claim:

1. A latch comprising:
a first AND-OR-invert (AOI) logic gate; and
a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node;
first and second n-type devices coupled in series;
a third n-type device coupled to the second n-type device at a storage node; and
first and second p-type devices coupled in parallel, the first and second p-type devices coupled to the storage node and the first keeper device, wherein the second n-type device and the first p-type device have their respective gate terminals coupled to a data node.

2. The latch of claim 1 , wherein the first n-type device and the first p-type device have their respective gate terminals coupled to a data node.

3. The latch of claim 2 , wherein the second n-type device and the second p-type device have their respective gate terminals coupled to a clock node.

4. The latch of claim 3 , wherein the first n-type device and the second p-type device have their respective gate terminals coupled to a clock node.

5. A latch comprising:
a first AND-OR-invert (AOI) logic gate; and
a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node;
wherein the second AOI logic gate comprises:
first and second n-type devices coupled in series;
a third n-type device coupled to the second n-type device at a storage node; and
first and second p-type devices coupled in parallel, the first and second p-type devices coupled to the storage node and the second keeper device.

6. The latch of claim 5 , wherein a gate terminal of the first keeper device is coupled to a gate terminal of the third n-type device of the first AOI logic gate and the storage node of the second AOI logic gate.

7. The latch of claim 5 , wherein a gate terminal of the second keeper device is coupled to a gate terminal of the third n-type device of the second AOI logic gate and the storage node of the first AOI logic gate.

8. The latch of claim 5 , wherein the first n-type device and the first p-type device of the second AOI logic gate have their respective gate terminals coupled to an output of an inverter.

9. The latch of claim 8 , wherein the second n-type device and the second p-type device of the second AOI logic gate have their respective gate terminals coupled to a clock node.

10. The latch of claim 5 , wherein the second n-type device and the first p-type device of the second AOI logic gate have their respective gate terminals coupled to an output of an inverter.

11. The latch of claim 10 , wherein the first n-type device and the second p-type device of the second AOI logic gate have their respective gate terminals coupled to a clock node.

12. The latch of claim 5 further comprises an inverter with an input node coupled to either the storage node of the first AOI logic gate or the storage node of the second AOI logic gate.

Assignees

• Hsu Steven K
• Agarwal Amit
• Krishnamurthy Ram K
• Intel Corp

Inventors

• Hsu Steven K
• Agarwal Amit
• Krishnamurthy Ram K

Classifications

• H03K3/35625 Primary

  using complementary field-effect transistors · CPC title

• H03K3/356104 Primary

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title