Apparatus and method for low power fully-interruptible latches and master-slave flip-flops

Patent metadata

Field	Value
Publication number	US-9960753-B2
Application number	US-201615209531-A
Country	US
Kind code	B2
Filing date	Jul 13, 2016
Priority date	Oct 31, 2013
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

First claim

We claim:

1. An apparatus, comprising:
a first AND-OR-invert (AOI) logic gate; and,
a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates comprise respective first and second keeper devices coupled to a power supply node;
a clock input signal line coupled to both the first and second AOI logic gates;
a data input signal line coupled to the first AOI logic gate and an inverted data input signal line coupled to the second AOI gate, wherein the inverted data input signal line is coupled to a first transistor of the second AOI gate that resides between the second keeper device and a second transistor of the second AOI gate that is also coupled to the inverted data input signal line.

2. The apparatus of claim 1 wherein the data input signal line is coupled to a first transistor of the first AOI gate that resides between the first keeper device and a second transistor of the first AOI gate that is also coupled to the data input signal line.

3. The apparatus of claim 2 wherein the first transistor of the AOI gate, the second transistor of the first AOI gate and a third transistor of the first AOI gate are coupled to an internal node of the first AOI gate.

4. The apparatus of claim 3 wherein the internal node is coupled to the first keeper device.

5. The apparatus of claim 3 wherein the internal node is coupled to the second keeper device.

6. The apparatus of claim 3 wherein the internal node is coupled to a gate node of the second keeper device and is coupled to a gate node of a third transistor that is a component of the second AOI logic gate, the third transistor coupled to the second transistor of the second AOI gate.

7. A computing system, comprising:
a processor;
a memory subsystem; a display;
circuitry comprising a) and b) below:
a) a first AND-OR-invert (AOI) logic gate; and,
b) a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates comprise respective first and second keeper devices coupled to a power supply node;

a data input signal line coupled to the first AOI logic gate and an inverted data input signal line coupled to the second AOI gate, wherein the data input signal line is coupled to a first transistor of the first AOI gate that resides between the first keeper device and a second transistor of the first AOI gate that is also coupled to the data input signal line.

8. The computing system of claim 7 further comprising a clock input signal line coupled to both the first and second AOI logic gates.

9. The computing system of claim 7 wherein the inverted data input signal is coupled to a first transistor of the second AOI gate that resides between the second keeper device and a second transistor of the second AOI gate that is also coupled to the second data input signal.

10. The computing system of claim 7 wherein the first transistor of the AOI gate, the second transistor of the first AOI gate and a third transistor of the first AOI gate are coupled to an internal node of the first AOI gate.

11. The computing system of claim 10 wherein the internal node is coupled to the first keeper device.

12. The computing system of claim 10 wherein the internal node is coupled to the second keeper device.

13. The computing system of claim 10 wherein the internal node is coupled to a gate node of the second keeper device and is coupled to a gate node of a third transistor that is a component of the second AOI logic gate, the third transistor coupled to the second transistor of the second AOI gate.

Assignees

• Intel Corp

Inventors

• Hsu Steven K
• Agarwal Amit
• Krishnamurthy Ram K

Classifications

• H03K3/356104

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H03K3/35625 Primary

  using complementary field-effect transistors · CPC title