EMIB patch on glass laminate substrate

Patent metadata

Field	Value
Publication number	US-12148703-B2
Application number	US-202318135067-A
Country	US
Kind code	B2
Filing date	Apr 14, 2023
Priority date	Mar 18, 2019
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.

First claim

What is claimed is:

1. An apparatus, comprising:
a glass layer;
first and second vias in the glass layer;
a first dielectric layer on the glass layer, wherein the first dielectric layer has a material composition different than a material composition of the glass layer;
conductive routing in the first dielectric layer, the conductive routing conductively coupled to at least one of the first and second via;
an interconnect bridge adjacent at least a portion of the first dielectric layer; and
a second dielectric layer over the first dielectric layer, wherein the second dielectric layer is over the interconnect bridge and along sidewalls of the interconnect bridge, and wherein the second dielectric layer is laterally intervening between the first dielectric layer and the interconnect bridge.

2. The apparatus of claim 1 , wherein a pitch between the first and second vias is between 80 and 200 microns.

3. The apparatus of claim 1 , further comprising:
a substrate, wherein the glass layer is over the substrate; and
interconnects conductively coupling the substrate to at least one of the first and second vias.

4. The apparatus of claim 3 , wherein the substrate comprises an interposer.

5. The apparatus of claim 1 , wherein the first dielectric layer comprises an organic material.

6. The apparatus of claim 1 , further comprising third and fourth vias in the second dielectric layer, wherein the third and fourth vias are conductively coupled to the interconnect bridge.

7. The apparatus of claim 6 , wherein a pitch between the third and fourth vias is between 20 and 60 microns.

8. The apparatus of claim 6 , further comprising:
first and second dies over the interconnect bridge.

9. The apparatus of claim 8 , wherein the third via conductively couples the first die to the interconnect bridge, and wherein the fourth via conductively couples the second die to the interconnect bridge.

10. The apparatus of claim 1 , wherein the glass layer has a thickness of at least 100 microns and no more than a millimeter.

11. The apparatus of claim 1 , further comprising a cavity in the first dielectric layer, wherein the interconnect bridge is in the cavity.

12. An apparatus, comprising:
a glass substrate, the glass substrate having a thickness greater than or equal to 100 microns and less than or equal to a millimeter;
first and second vias in the glass substrate, the first and second vias being spaced apart by a distance of between 80 and 200 microns;
a first dielectric layer over the glass substrate, the first dielectric layer comprising a material different than a material of the glass substrate;
metal routing in the first dielectric layer, the metal routing conductively coupled to the first and second vias;
a bridge die adjacent at least a portion of the first dielectric layer;
a second dielectric layer over the first dielectric layer and over the bridge die, wherein the second dielectric layer is along sidewalls of the bridge die, and wherein the second dielectric layer is laterally intervening between the first dielectric layer and the bridge die; and
third and fourth vias in the second dielectric layer, the third and fourth vias conductively coupled to the bridge die, the third and fourth vias being spaced apart by a distance of between 20 and 60 microns.

13. The apparatus of claim 12 , further comprising a cavity in the first dielectric layer, wherein the bridge die is in the cavity.

14. The apparatus of claim 12 , further comprising:
first and second dies over the bridge die, wherein the first die is conductively coupled to the bridge die by the third via, and wherein the second die is conductively coupled to the bridge die by the fourth via.

15. The apparatus of claim 14 , wherein the metal routing conductively couples at least one of the first and second vias to at least one of the first and second dies.

16. The apparatus of claim 12 , wherein the bridge die comprises an embedded multi-die interconnect bridge die.

17. An apparatus, comprising:
a glass layer;
a first dielectric layer over the glass layer, the first dielectric layer comprising a material different than a material of the glass layer;
first and second dies over the first dielectric layer;
die bridging means over the glass layer and under the first and second dies, the die bridging means for conductively coupling the first die to the second die; and
a second dielectric layer over the first dielectric layer, wherein the second dielectric layer is over the die bridging means and along sidewalls of the die bridging means, and wherein the second dielectric layer is laterally intervening between the first dielectric layer and the die bridging means.

18. The apparatus of claim 17 , wherein the die bridging means comprises an interconnect bridge die.

19. The apparatus of claim 17 , wherein the glass layer has a thickness of greater than or equal to 100 microns and less than or equal to a millimeter.

Assignees

• Intel Corp

Inventors

• Sankman Robert
• May Robert

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title