Packaging structure and manufacturing method thereof

US11309283B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11309283-B2
Application numberUS-202017099801-A
CountryUS
Kind codeB2
Filing dateNov 17, 2020
Priority dateDec 31, 2019
Publication dateApr 19, 2022
Grant dateApr 19, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A packaging structure includes a bridge die, a through silicon via die, a first encapsulant, a first active die, a second active die, a second encapsulant, and a redistribution circuit structure. The first encapsulant covers the through silicon via die and the bridge die. The first active die is electrically connected to the bridge die and the through silicon via die. The second active die is electrically connected to the bridge die. The second encapsulant covers the first active die and the second active die. The redistribution circuit structure is electrically connected to the through silicon via die. The through silicon via die is disposed between the first active die and the redistribution circuit structure. A manufacturing method of a packaging structure is also provided.

First claim

Opening claim text (preview).

What is claimed is: 1. A packaging structure, comprising: a bridge die; a through silicon via die, comprising a first the through silicon via die, wherein the first the through silicon via die comprises a plurality of first through silicon conductors and a plurality of second through silicon conductors; a first encapsulant, covering the through silicon via die and the bridge die; a first active die, electrically connected to the bridge die and the through silicon via die; a second active die, electrically connected to the bridge die; a passive device, electrically connected to the first the through silicon via die; a second encapsulant, covering the first active di; the second active die and the passive device; and a redistribution circuit structure, electrically connected to the through silicon via die, wherein: the through silicon via die is disposed between the first active die and the redistribution circuit structure; the plurality of first through silicon conductors are overlapped on the first active die, and a first spacing exists between the plurality of first through silicon conductors; the plurality of second through silicon conductors are overlapped on the passive device, and a second spacing exists between the plurality of second through silicon conductors; and the second spacing is greater than or equal to the first spacing. 2. The packaging structure according to claim 1 , wherein: the first active die comprises a first active surface; the second active die comprises a second active surface; the through silicon via die comprises a first connection surface and a second connection surface opposite to the first connection surface; the bridge die comprises a bridge connection surface and a bridge back surface opposite to the bridge connection surface; the bridge connection surface faces the first active surface and the second active surface; the first connection surface faces the first active surface; and the redistribution circuit structure is at least disposed on the second connection surface. 3. The packaging structure according to claim 2 , wherein: the first encapsulant comprises a first encapsulation surface and a second encapsulation surface opposite to the first encapsulation surface; the first encapsulation surface faces the second encapsulant; and the second connection surface, the bridge back surface, and the second encapsulation surface are substantially coplanar. 4. The packaging structure according to claim 3 , wherein the through silicon via die comprises: a silicon substrate; and a through silicon conductor, penetrating the silicon substrate, and comprising a conductive core layer and an insulating shell layer laterally coating the conductive core layer, wherein a partial surface of the silicon substrate, a partial surface of the conductive core layer, and a partial surface of the insulating shell layer are substantially coplanar and construct at least one part of the second connection surface. 5. The packaging structure according to claim 2 , wherein the through silicon via die comprises: a silicon substrate; a through silicon conductor, penetrating the silicon substrate, and comprising a conductive core layer and an insulating shell layer laterally coating the conductive core layer; and; a connection pad, disposed on the silicon substrate and comprising a conductive connection layer, wherein the conductive core layer and the conductive connection layer are same films. 6. The packaging structure according to claim 1 , wherein the bridge die comprises: a silicon substrate; and an interconnection structure, disposed on the silicon substrate, and comprising a plurality of conductive layers and an insulating layer clamped between the plurality of conductive layers. 7. The packaging structure according to claim 1 , wherein the bridge die is disposed between the second active die and the redistribution circuit structure. 8. The packaging structure according to claim 1 , wherein the first encapsulant and the second encapsulant physically contact. 9. The packaging structure according to claim 1 , further comprising: a heat dissipation member, at least thermally coupled to the first active die or the second active die. 10. A manufacturing method of a packaging structure, comprising: providing a through silicon via die and a bridge die, wherein the through silicon via die comprises a first the through silicon via die, and the first the through silicon via die comprises a plurality of first through silicon conductors and a plurality of second through silicon conductors; forming a first encapsulant covering the through silicon via die and the bridge die; forming a redistribution circuit structure electrically connected to the through silicon via die; configuring a first active die electrically connected to the bridge die and the through silicon via die; configuring a second active die electrically connected to the bridge die; configuring a passive device electrically connected to the first the through silicon via die; and forming a second encapsulant covering the first active die, the second active die, and the passive device, wherein after the step of forming the redistribution circuit structure and the step of configuring the first active die, the through silicon via die is disposed between the first active die and the redistribution circuit structure, wherein after the step of configuring the first active die and the step of configuring a passive device electrically connected to the first the through silicon via die, the plurality of first through silicon conductors are overlapped on the first active die and the plurality of second through silicon conductors are overlapped on the passive device, wherein a first spacing exists between the plurality of first through silicon conductors, a second spacing exists between the plurality of second through silicon conductors and the second spacing is greater than or equal to the first spacing. 11. The manufacturing method of the packaging structure according to claim 10 , wherein: the step of providing the through silicon via die and the bridge die comprises configuring the through silicon via die and the bridge die on a first carrier board; and the step of forming the first encapsulant comprises forming the first encapsulant on the carrier board, and removing the first carrier board before configuring the first active die or the second active die. 12. The manufacturing method of the packaging structure according to claim 10 , further comprising: before configuring the first active die or the second active die, placing the through silicon via die, the bridge die, the first encapsulant, and the redistribution circuit structure on a second carrier board, and at least locating the redistribution circuit structure between the through silicon via die and the second carrier board; after forming the second encapsulant, removing the second carrier board. 13. The manufacturing method of the packaging structure according to claim 10 , wherein the step of forming the first encapsulant comprises: forming a first encapsulation material to cover the through silicon via die and the bridge die; and performing a first thinning process, to remove a part of the first encapsulation material, to form a first encapsulant laterally covering the through silicon via die and the bridge die, and expose the through silicon via die and the bridge die. 14. The manufacturing method of the packaging structure according to claim 10 , wherein the step of forming the second encapsulant comprises: forming a second encapsulation material to cover

Assignees

Inventors

Classifications

  • the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

  • at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

  • Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

  • H10W90/00Primary

    Package configurations · CPC title

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Frequently asked questions

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What does patent US11309283B2 cover?
A packaging structure includes a bridge die, a through silicon via die, a first encapsulant, a first active die, a second active die, a second encapsulant, and a redistribution circuit structure. The first encapsulant covers the through silicon via die and the bridge die. The first active die is electrically connected to the bridge die and the through silicon via die. The second active die is e…
Who is the assignee on this patent?
Powertech Technology Inc
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 19 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).