Semiconductor package with through bridge die connections

Patent metadata

Field	Value
Publication number	US-10950550-B2
Application number	US-201515774306-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	Dec 22, 2015
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.

First claim

The claimed invention is:

1. A semiconductor package, comprising:
a first build-up layer with a top surface and a bottom surface opposing the top surface, the first build-up layer having a power contact on the top surface of the first build-up layer;
a second build-up layer overlying the first build-up layer, the second build-up layer defining a void overlying the power contact;
a bridge die disposed within the void of the second build-up layer, the bridge die having a bridge die backside and a bridge die topside, the bridge die topside having a plurality of bridge die topside contacts, the bridge die backside electrically coupled to the power contact; and
a third build-up layer disposed overlying the topside of the bridge die and over the second build-up layer, the third build-up layer having an interconnect trace, the interconnect trace electrically coupled to a first bridge die topside contact of the plurality of bridge die topside contacts.

2. The semiconductor package of claim 1 , further comprising a conductive adhesive disposed between the power contact and the bridge die backside.

3. The semiconductor package of claim 2 , wherein the bridge die backside comprises a bridge die backside metal layer, and wherein the conductive adhesive contacts the bridge die backside metal.

4. The semiconductor package of claim 1 , further comprising a die disposed on the third build-up layer and electrically connected to the interconnect trace.

5. The semiconductor package of claim 4 , wherein the die is a first die, and further comprising a second die disposed on the third build-up layer, wherein the first die is electrically coupled to the second die via the interconnect trace.

6. The semiconductor package of claim 4 , wherein the interconnect trace is a first interconnect trace, wherein the die is electrically connected to the first interconnect trace via a first die-to-package connect, wherein the die is further electrically connected to a second interconnect trace of the third build-up layer via a second die-to-package connect, and wherein the second die-to-package connect has a greater size than the first die-to-package connect.

7. The semiconductor package of claim 1 , wherein the first bridge die topside contact is electrically coupled to the bridge die backside by a bridge die via a bridge die bulk.

8. The semiconductor package of claim 1 , wherein the void is a first void, and further comprising a fourth build-up layer disposed over the second build-up layer and under the third build-up layer, the fourth build-up layer having a second void overlying the power contact, and wherein the first void and the second void define a cavity in which the bridge die is disposed.

9. The semiconductor package of claim 1 , wherein the bridge die comprises a bulk portion electrically coupled to a backside metal provided on the bridge die backside, and wherein at least one of the plurality of bridge die topside contacts is electrically coupled to the bulk portion to conduct power through the bulk portion of the bridge die to the at least one of the plurality of bridge die topside contacts and to one or more dies electrically connected to the at least one of the plurality of bridge die topside contacts.

10. The semiconductor package of claim 1 , further comprising a fourth build-up layer.

11. The semiconductor package of claim 1 , further comprising:
a package core, the package core having a top package core surface and a bottom package core surface;
a fourth build-up layer formed on the bottom package core surface; and one or more package-to-board contacts electrically coupled to the fourth build-up layer.

12. A method, comprising:
forming a first build-up layer, the first build-up layer having a power contact;
forming one or more second build-up layers overlying the first build-up layer;
removing portions of the one or more second build-up layers to form a cavity in the one or more second build-up layers;
providing a bridge die within the cavity, wherein a backside of the bridge die is electrically connected to the power contact, the bridge die having a bridge die topside contact;
forming one or more third build-up layers overlying the bridge die and the one or more second build-up layers, a first of the one or more third build-up layers having an interconnect electrically coupled to the bridge die topside contact; and
attaching a first die and a second die to interconnects provided on the one or more third build-up layers.

13. The method of claim 12 , further comprising cutting through the first build-up layer, the one or more second build-up layers, and the one or more third build-up layers to singulate a semiconductor package having the bridge die.

14. The method of claim 12 , wherein forming the first build-up layer comprises forming the first build-up layer on a topside of a package core.

15. The method of claim 14 , further comprising:
forming one or more fourth build-up layers on the bottom side of the package core; and
forming one or more package-to-board connections on the one or more fourth build-up layers.

16. The method of claim 12 , wherein removing the portions of the one or more second build-up layers further comprises laser ablating the portions of the one or more second build-up layers to expose the power contact underlying the one or more second build-up layers.

17. The method of claim 12 , further comprising depositing a conductive adhesive within the cavity.

18. The method of claim 12 , wherein providing the bridge die within the cavity further comprises aligning the bridge die over the cavity and then placing the bridge die within the cavity, wherein a volume of the cavity is greater than a volume of the bridge die.

19. The method of claim 12 , wherein providing the bridge die within the cavity further comprises:
doping a wafer;
forming one or more bulk contacts on a topside of the wafer;
forming one or more metal interconnect layers over the one or more bulk contacts;
thinning the wafer on a bottom side of the wafer;
depositing backside metal on the bottom side of the wafer; and
singulating the wafer to form the bridge die.

20. The method of claim 19 , wherein thinning the wafer comprises thinning the wafer to a thickness that is substantially equal to the thickness of the one or more second build-up layers.

21. The method of claim 12 , wherein attaching a first die comprises:
connecting a first contact of the first die to a first pad on the one or more third build-up layers; and
connecting a second contact of the first die to a second pad on the one or more third build-up layers, wherein the first pad has a smaller area than the second pad, and wherein the first pad overlies the bridge die and the second pad does not overlie the bridge die.

22. A method, comprising:
forming a first build-up layer, the first build-up layer having a power contact;
forming one or more second build-up layers overlying the first build-up layer;
removing portions of the one or more second build-up layers to form a cavity in the one or more second build-up layers;
providing a bridge die within the cavity, wherein a backside of the bridge die is electrically connected to the power contact;
forming one or more third build-up layers overlying the bridge die and the one or more second build-up layers;
attaching a first die and a second die to interconnects provided on the one or more third build-up layers; and
cutting through the first build-up layer, the one or m

Assignees

• Intel Corp

Inventors

• Qian Zhiguo
• Xie Jianyong
• Aygun Kemal

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/0198

  batch processes · CPC title