Non-volatile memory device including multi-stack memory block and operating method thereof

Patent metadata

Field	Value
Publication number	US-12147666-B2
Application number	US-202218052428-A
Country	US
Kind code	B2
Filing date	Nov 3, 2022
Priority date	Nov 10, 2021
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

According to an example embodiment of the inventive concepts, an operating method of a memory system including a memory controller and a non-volatile memory device, the non-volatile memory device being operated under control by the memory controller and the non-volatile memory including a first memory block and a second memory block, the method includes determining, by the memory controller, whether the first memory block satisfies a block reset condition, in response to the first memory block satisfying the block reset condition, applying a turn-on voltage to word lines of dummy cells included in the first memory block, transferring data pre-programmed in the first memory block to the second memory block, erasing the first memory block, and re-programming the dummy cells of the first memory block.

First claim

What is claimed is:

1. An operating method of a memory system comprising a memory controller and a non-volatile memory device, the non-volatile memory device being operated under control of the memory controller, and the non-volatile memory device comprising a first memory block and a second memory block, the method comprising:
determining, by the memory controller, whether the first memory block satisfies a block reset condition;
in response to the first memory block satisfying the block reset condition, applying a turn-on voltage to word lines of dummy cells included in the first memory block;
transferring data pre-programmed in the first memory block to the second memory block;
erasing the first memory block; and
re-programming the dummy cells of the first memory block.

2. The method of claim 1 , wherein the determining of whether the first memory block satisfies the block reset condition, by the memory controller, comprises:
in response to a voltage level of a threshold voltage of the dummy cells included in the first memory block being less than zero or greater than a voltage level of a first reference voltage, determining that the first memory block satisfies the block reset condition,
wherein the voltage level of the first reference voltage has a threshold value at which the first memory block is capable of performing a read operation.

3. The method of claim 2 , wherein a voltage level of the first reference voltage is equal to a first voltage level of a threshold voltage of memory cells included in the first memory block in response to a first amount of data being programmed in the memory cells.

4. The method of claim 1 , wherein a voltage level of the turn-on voltage is greater than a first voltage level of a read voltage applied to word lines of memory cells included in the first memory block during a read operation.

5. The method of claim 1 , wherein the second memory block comprises a memory block that does not satisfy the block reset condition.

6. An operating method of a non-volatile memory device, the non-volatile memory device comprising a first memory block, a second memory block and a third memory block, each of the first memory block, the second memory block and the third memory block comprising a first sub-block, a second sub-block, and a dummy block, the first sub-block comprising a first plurality of memory cells, the second sub-block comprising a second plurality of memory cells, and the dummy block comprising a plurality of dummy cells, the second sub-block being arranged on the first sub-block, and the dummy block being arranged between the first sub-block and the second sub-block, the method comprising:
receiving a command for the first memory block to perform a first operation; and
in response to the first memory block satisfying a block reset condition, performing a block reset operation on the first memory block, wherein the performing of the block reset operation comprises:
applying a turn-on voltage to dummy word lines included in the dummy block of the first memory block,
transferring, to the second memory block, data previously programmed in the first sub-block or the second sub-block of the first memory block,
performing an erase operation entirely on the first memory block, and
re-programming the dummy cells of the first memory block.

7. The method of claim 6 , wherein
the block reset condition is satisfied when a voltage level of a threshold voltage of the dummy cells of the first memory block is less than zero or greater than a voltage level of a first reference voltage, and
the voltage level of the first reference voltage has a threshold value at which the first memory block is capable of performing a read operation.

8. The method of claim 6 , wherein a voltage level of the turn-on voltage is greater than a first voltage level of a read voltage applied to word lines of memory cells of the first memory block during a read operation.

9. The method of claim 6 , wherein the second memory block and the third memory block do not satisfy the block reset condition.

10. The method of claim 6 , wherein the command comprises an erase command for the first sub-block or the second sub-block of the first memory block, the first sub-block being a sub-block to be erased, and,
the method further comprising
in response to the first memory block not satisfying the block reset condition, performing of the first operation by the first memory block based on the command by applying, to the dummy word lines of the first memory block, a voltage for not injecting a hole into the second sub-block or the first sub-block of the first memory block, the second sub-block being a sub-block not to be erased.

11. The method of claim 6 , wherein
the second sub-block of the first memory block contains data which was previously programmed,
the command comprises a program command for the first sub-block of the first memory block,
the method further comprising
in response to the first memory block not satisfying the block reset condition, performing of the first operation by the first memory block based on the command by applying a block pass voltage to word lines included in the second sub-block of the first memory block and the dummy word lines of the first memory block, wherein a voltage level of the block pass voltage is equal to a voltage level of the turn-on voltage.

12. The method of claim 11 , further comprising,
in response to the first memory block satisfying the block reset condition, programming, in the second memory block, data that is to be programmed in the first sub-block of the first memory block, before the block reset operation is performed,
wherein the transferring of the data previously programmed in the first memory block to the second memory block comprises transferring the data previously programmed in the second sub-block of the first memory block to an unprogrammed sub-block of the second memory block.

13. The method of claim 6 , wherein
the first sub-block of the first memory block has previously programmed data thereon,
the command comprises a program command for the second sub-block of the first memory block, and
the method further comprises
in response to the first memory block satisfying a dummy block turn-off condition, applying a turn-off voltage to the dummy word lines of the first memory block; and
in response to the first memory block not satisfying the dummy block turn-off condition, determining whether the first memory block satisfies the block reset condition.

14. The method of claim 13 , wherein
the dummy block turn-off condition is satisfied if a voltage level of a threshold voltage of the dummy cells of the first memory block is less than zero or greater than a voltage level of a second reference voltage, and
the voltage level of the second reference voltage has a threshold value at which the dummy cells of the first memory block are capable of electrically blocking the first sub-block of the first memory block and the second sub-block of the first memory block.

15. The method of claim 13 , further comprising:
in response to the first memory block not satisfying the block reset condition, applying the turn-on voltage to the dummy word lines of the first memory block before the first memory block performs the first operation based on the command; and
in response to the first memory block satisfying the block reset condition, programming, in the second memory block, data that is to be programmed in the second sub-block of the first memory block, before the first memory block performs the block reset operation,
wherein the transferrin

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Yohan
• Yu Jaeduk
• Cho Jiho

Classifications

• G06F3/064

  Management of blocks · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title