Methods of operating nonvolatile memory devices including erasing a sub-block

Patent metadata

Field	Value
Publication number	US-10283204-B2
Application number	US-201715607551-A
Country	US
Kind code	B2
Filing date	May 29, 2017
Priority date	Nov 22, 2016
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

In a method of operating a nonvolatile memory device, a first sub-block to be erased is selected in a first memory block including the first sub-block and a second sub-block adjacent to the first sub-block, in response to a erase command and an address. The first sub-block includes memory cells connected to a plurality of word-lines including at least one boundary word-line adjacent to the second sub-block and internal word-lines other than the at least one boundary word-line. An erase voltage is applied to a substrate in which the first memory block is formed. Based on a voltage level of the erase voltage applied to the substrate, applying, a first erase bias condition to the at least one boundary word-line and a second erase bias condition different from the first erase bias condition to the internal word-lines during an erase operation being performed on the first sub-block.

First claim

What is claimed is:

1. A method of operating a nonvolatile memory device, the method comprising:
selecting a first sub-block to be erased in a first memory block including the first sub-block and a second sub-block, adjacent to the first sub-block, in response to an erase command and an address, wherein the first sub-block includes memory cells connected to a plurality of word-lines including at least one boundary word-line adjacent to the second sub-block and internal word-lines other than the at least one boundary word-line, and wherein each of the memory cells connected to the at least one boundary word-line stores a plurality of bits;
applying an erase voltage to a substrate in which the first memory block is formed; and
based on a voltage level of the erase voltage applied to the substrate, applying a first erase bias condition to the at least one boundary word-line and a second erase bias condition different from the first erase bias condition to the internal word-lines during an erase operation being performed on the first sub-block,
wherein the voltage level of the erase voltage applied to the substrate increases with a constant slope during a first interval and the voltage level of the erase voltage applied to the substrate is maintained at a constant level during a second interval successive to the first interval,
wherein the first erase bias condition comprises applying a word-line erase voltage to the at least one boundary word-line during the first interval and floating the at least one boundary word-line at a first time point in the first interval or in the second interval, and
wherein the second erase bias condition comprises applying the word-line erase voltage to the internal word-lines during the first and second intervals.

2. The method of claim 1 , wherein the first time point corresponds to a time point at which the voltage level of the erase voltage applied to the substrate reaches a reference voltage level.

3. The method of claim 1 , wherein a level of the erase voltage is higher than a level of the word-line erase voltage and the word-line erase voltage is a ground voltage or higher than the ground voltage.

4. The method of claim 1 , wherein the word-line erase voltage is applied to the internal word-lines until a second time point in the second interval and the at least one boundary word-line is floated until the second time point in the second interval.

5. The method of claim 4 , further comprising:
floating word-lines of unselected sub-blocks in the first memory block other than the first sub-block during the second interval.

6. The method of claim 1 ,
wherein the first erase bias condition further comprises cutting off an application of the erase voltage at a second time point in the second interval, wherein the second time point is later than the first time point, and
wherein the second erase bias condition further comprises cutting off an application of the erase voltage at the second time point in the second interval.

7. The method of claim 6 , wherein the word-line erase voltage is applied to the internal word-lines and the at least one boundary word-line until the first time point in the second interval.

8. The method of claim 6 , further comprising:
floating word-lines of unselected sub-blocks in the first memory block other than the first sub-block during the first interval and the second interval.

9. The method of claim 6 , wherein a first erase execution time taken for erasing memory cells coupled to the at least one boundary word-line is smaller than a second erase execution time taken for erasing memory cells coupled to each of the internal word-lines.

10. The method of claim 1 , wherein:
the first memory block comprises a plurality of cell strings,
each of the plurality of cell strings comprises a plurality of memory cells stacked in a vertical direction which is perpendicular to the substrate,
the first sub-block and the second sub-block are adjacent to each other in the vertical direction, and
the at least one boundary word-line corresponds to a normal word-line coupled to normal memory cells.

11. A method of operating a nonvolatile memory device including a plurality of memory cells, each storing a plurality of bits, the method comprising:
performing a program operation for a first memory block including a plurality of sub-blocks, each sub-block including memory cells coupled to a plurality of word-lines, wherein performing the program operation includes:
programming p-bit data in each memory cell of first memory cells coupled to at least one boundary word-line of the plurality of word-lines; and
programming q-bit data in each memory cell of second memory cells coupled to each of internal word-lines other than the at least one boundary word-line of the plurality of word-lines,
wherein the at least one boundary word-line is adjacent to another sub-block, p is a natural number greater than 1 and q is a natural number greater than p; and

performing an erase operation for a first sub-block in the first memory block including the first sub-block and a second sub-block adjacent to the first sub-block, wherein performing the erase operation includes:
based on a voltage level of an erase voltage applied to a substrate in which the first memory block is formed, applying a first erase bias condition to the at least one boundary word-line and a second erase bias condition different from the first erase bias condition to the internal word-lines,

wherein the voltage level of the erase voltage applied to the substrate increases with a constant slope during a first interval and the voltage level of the erase voltage applied to the substrate is maintained at a target level during a second interval successive to the first interval,
wherein the first erase bias condition comprises applying a word-line erase voltage smaller than the erase voltage to the at least one boundary word-line of the first sub-block until a first time point in the first interval and floating the at least one boundary word-line from the first time point in the first interval or in the second interval, and
wherein the second erase bias condition comprises applying the word-line erase voltage to the internal word-lines of the first sub-block during the first interval and the second interval.

12. The method of claim 11 ,
wherein the first erase bias condition further comprises cutting off an application of the erase voltage at a second time point in the second interval, wherein the second time point is later than the first time point, and
wherein the second erase bias condition further comprises cutting off an application of the erase voltage at the second time point in the second interval.

13. The method of claim 11 , wherein
the first memory block comprises a plurality of cell strings,
each of the plurality of cell strings comprises a plurality of memory cells stacked in a vertical direction which is perpendicular to the substrate,
the first sub-block and the second sub-block are adjacent to each other in the vertical direction, and
the at least one boundary word-line corresponds to a normal word-line coupled to normal memory cells.

14. A method of operating a nonvolatile memory device including a memory cell array including a plurality of memory blocks, each memory block including a plurality of sub-blocks, each sub-block including a plurality of memory cells, the method comprising:
performing an erase operation for a first sub-block of a first memory block, wherein performing the erase operation comprises:
applying an erase voltage to a substrate in which the first memory block is disposed;
applying

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Chang-Min
• Kim Dong-Chan
• Lee Ae-Jeong
• Choi Moo-Rym

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G11C11/5635

  Erasing circuits · CPC title

• G11C16/225 Primary

  Preventing erasure, programming or reading when power supply voltages are outside the required ranges · CPC title