Nonvolatile memory device and method of performing an erase operation in the same

Patent metadata

Field	Value
Publication number	US-10614889-B2
Application number	US-201816176117-A
Country	US
Kind code	B2
Filing date	Oct 31, 2018
Priority date	Jan 16, 2018
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

An erase voltage is applied to channels of a selected string group to erase only the selected string group. A size and a number of the spare blocks for storing meta data are reduced and thus a size of the nonvolatile memory device is reduced by reducing unit capacity of the erase operation through grouping of the cell strings. Lifetime of the nonvolatile memory device is extended by having control over erasing some cell strings and not others. Control of cell strings for erasure includes allowing some control lines to float, in some embodiments. In some embodiments, ground select transistors with different thresholds and appropriately applied voltages are used to control erasure of particular cell strings. In some embodiments, biasing of word lines is applied differently to portions of a particular cell string to only erase a portion of the particular cell string.

First claim

What is claimed is:

1. A method of performing an erase operation in a nonvolatile memory device including a memory block, the memory block including a plurality of cell strings, the plurality of cell strings including a first string group and a second string group, the first string group including a first plurality of memory cells disposed in a vertical direction, the second string group including a second plurality of memory cells disposed in the vertical direction, wherein the first string group is associated with first channels and the second string group is associated with second channels, the method comprising:
forming an erase address corresponding to the first string group; and
only applying, based on the erase address, an erase voltage to at least a portion of the first channels and not applying the erase voltage to the second channels.

2. The method of claim 1 , wherein the only applying, based on the erase address, an erase voltage to at least a portion of the first channels and not applying the erase voltage to the second channels comprises:
applying the erase voltage to a common source line of the plurality of cell strings;
turning on first ground selection transistors of the first string group while applying the erase voltage to the common source line; and
turning off second ground selection transistors of the second string group.

3. The method of claim 1 , wherein the only applying, based on the erase address, an erase voltage to at least a portion of the first channels and not applying the erase voltage to the second channels comprises:
applying the erase voltage to bit lines of the plurality of cell strings;
turning on first string selection transistors of the first string group while applying the erase voltage to the bit lines; and
turning off second string selection transistors of the second string group.

4. The method of claim 1 , wherein the only applying, based on the erase address, an erase voltage to at least a portion of the first channels and not applying the erase voltage to the second channels comprises:
applying the erase voltage to a common source line of the plurality of cell strings;
applying the erase voltage to bit lines of the plurality of cell strings;
turning on first ground selection transistors of the first string group;
turning on first string selection transistors of the first string group;
turning off second ground selection transistors of the second string group; and
turning off second string selection transistors of the second string group.

5. The method of claim 2 , wherein the turning on first ground selection transistors comprises applying a first control signal to first ground selection lines in a gate layer, wherein the gate layer includes first ground selection transistors; and wherein the first ground selection lines are coupled to first gate electrodes of the first ground selection transistors.

6. The method of claim 5 , wherein the only applying, based on the erase address, an erase voltage to at least a portion of the first channels and not applying the erase voltage to the second channels comprises:
applying the erase voltage to a common source line of the plurality of cell strings;
maintaining a first voltage of a first ground selection line corresponding to the first string group at a turn-on voltage lower than a reference voltage, the reference voltage corresponding to the erase voltage minus a threshold voltage of the first ground selection transistors; and
maintaining a second voltage of a second ground selection line corresponding to the second string group at a turn-off voltage higher than the reference voltage.

7. The method of claim 6 , wherein the first ground selection line is floated after a reference delay time is elapsed from a time point when applying the erase voltage to the common source line, and the second ground selection line is floated before the reference delay time is elapsed.

8. The method of claim 6 , wherein the turn-on voltage is applied to the first ground selection line as a bias voltage while applying the erase voltage to the common source line, and the turn-off voltage is applied to the second ground selection line as a bias voltage while applying the erase voltage to the common source line.

9. The method of claim 1 , wherein the only applying, based on the erase address, an erase voltage to at least a portion of the first channels and not applying the erase voltage to the second channels comprises:applying a turn-on voltage VGON lower than a reference voltage VREF to a first gate electrode of a first ground selection transistor of the first string group, wherein VREF is equal to the erase voltage minus a transistor threshold voltage; and
applying a turn-on voltage VGOFF higher than a reference voltage VREF to a second gate electrode of a second ground selection transistor of the second string group.

10. The method of claim 9 , wherein the only applying, based on the erase address, an erase voltage to at least a portion of the first channels and not applying the erase voltage to the second channels comprises: applying VGON after applying VGOFF.

11. The method of claim 1 , wherein:
the first string group comprises a plurality of sub blocks disposed in the vertical direction, and
the memory block includes a plurality of intermediate switching transistors disposed in a boundary layer between the plurality of sub blocks.

12. The method of claim 11 , further comprising:
selectively switching the plurality of intermediate switching transistors by units of string groups based on the erase address and an end of the memory block from which the erase voltage is applied; and
selectively erasing one of a first group segment of the first string group under the boundary layer and a second group segment of the first string group over the boundary layer based on the erase address.

13. The method of claim 12 , wherein the selectively switching the plurality of intermediate switching transistors comprises:
turning off the intermediate switching transistors of the first string group when the erase voltage is applied to a common source line of the plurality of cell strings and only the first group segment of the first string group is erased; and
turning on the intermediate switching transistors of the first string group when the erase voltage is applied to the common source line and the second group segment of the first string group is erased.

14. The method of claim 12 , wherein the selectively switching the plurality of intermediate switching transistors comprises:
turning on the intermediate switching transistors of the first string group when the erase voltage is applied to bit lines of the plurality of cell strings and the first group segment of the first string group is erased; and
turning off the intermediate switching transistors of the first string group when the erase voltage is applied to the bit lines and only the second group segment of the first string group is erased.

15. The method of claim 12 , wherein the selectively switching the plurality of intermediate switching transistors comprises turning off all of the intermediate switching transistors of the plurality of cell strings when the erase voltage is applied to a common source line and bit lines of the plurality of cell strings and only one of the first group segment of the first string group and the second group segment of the first string group.

16. The method of claim 15 , wherein the only applying, based on the erase address, an erase voltage to at least a portion of the first channels and not applying the erase voltage to the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ko Kui-Han
• Kim Jin-Young
• Lim Bong-Soon
• Park Il-Han

Classifications

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C11/5635

  Erasing circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title