Self aligned buried power rail

Patent metadata

Field	Value
Publication number	US-12142516-B2
Application number	US-202217678437-A
Country	US
Kind code	B2
Filing date	Feb 23, 2022
Priority date	Apr 7, 2017
Publication date	Nov 12, 2024
Grant date	Nov 12, 2024

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

First claim

What is claimed:

1. A structure comprising:
gap fill insulator material separating and between a partial fin structure and one additional fin structure;
a buried power rail aligned with and over the partial fin structure and adjacent to the one additional fin structure; and
a contact to the buried power rail,
wherein the gap fill insulator material directly contacts the buried power rail, the partial fin structure and the one additional fin structure, and extends to a height planar with the buried power rail, above a top surface of the partial fin structure and below a top surface of the one additional fin structure, and
the partial fin structure and the one additional fin structure comprise a same semiconductor substrate.

2. The structure of claim 1 , wherein the semiconductor substrate comprises Si material.

3. The structure of claim 1 , wherein the buried power rail comprises conductive metal fill material, lined with dielectric material and a metal liner, the dielectric material contacting a top surface of the partial fin structure.

4. The structure of claim 1 , further comprising neighboring fin structures adjacent to the buried power rail, wherein a distance between the buried power rail and the neighboring fin structures is substantially equal to fin to fin spacing.

5. The structure of claim 1 , wherein the buried power rail is a metal fill material over a liner of conductive barrier material and the gap fill insulator material directly contacts the liner and directly contacts side surfaces of both the partial fin structure and the one additional fin structure.

6. The structure of claim 5 , wherein the liner of conductive barrier material is a multi-layer liner.

7. The structure of claim 6 , wherein the multi-layer liner comprises a first dielectric film to isolate electrically the semiconductor substrate and a single or bi-layer of barrier material.

8. The structure of claim 7 , wherein the single or bi-layer of barrier material is one of TaN, TiN, Co or Ru.

9. The structure of claim 5 , wherein the metal fill material is a high melting temperature metal.

10. The structure of claim 5 , further comprising a capping material on exposed surfaces of the metal fill material and the liner.

11. The structure of claim 10 , further comprising a gap fill material on the capping material.

12. The structure of claim 11 , wherein the gap fill material is recessed and a contact is within the recessed gap fill material contacting to the capping material on top of the buried power rail.

13. The structure of claim 1 , wherein the buried power rail is partially recessed within the partial fin structure.

14. The structure of claim 1 , wherein the partial fin structure is of a first height and the one additional fin structure comprises a second height higher than the first height.

15. The structure of claim 1 , wherein the buried power rail is recessed below a surface of the one additional fin structure and includes a portion extending below a surface of the partial fin structure.

16. The structure of claim 15 , wherein the buried power rail has a different dimension than the one additional fin structure.

17. The structure of claim 16 , wherein the buried power rail comprises a liner material and metal fill material, the liner material comprises insulator material that isolates the metal fill material from the partial fin structure.

18. The structure of claim 17 , further comprising a capping material over the liner material and the metal fill material, the capping material being a barrier material that has an exposed portion contacting the contact.

19. The structure of claim 1 , wherein the contact is wider than the buried power rail and contacts a top surface of a liner of the buried power rail.

20. The structure of claim 1 , further comprising gate material contacting the top surface of and side surfaces of the one additional fin structure and a top surface of the gap fill insulator material, the gate material being isolated from the buried power rail by insulator material and the gap fill insulator material.

Assignees

• Globalfoundries Us Inc

Inventors

• Licausi Nicholas V
• Bouche Guillaume
• Liebmann Lars W

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/021 Primary

  of interconnections within wafers or substrates · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D84/834

  comprising FinFETs · CPC title