Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2016104645-A1
Application number	US-201414536696-A
Country	US
Kind code	A1
Filing date	Nov 10, 2014
Priority date	Oct 14, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.

First claim

1 . A method for fabricating semiconductor device, comprising:
providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.

2 . The method of claim 1 , further comprising:
forming an interlayer dielectric (ILD) layer around the gate structures, wherein the top surface of the ILD layer is even with the top surface of the first stop layer; forming a second dielectric layer on the first stop layer; forming a patterned hard mask on the second dielectric layer; using the patterned hard mask to remove part of the second dielectric layer for forming a third opening to expose the ILD layer and the gate structures; using the patterned hard mask to remove part of the ILD layer for forming a plurality of contact holes; and forming a plurality of first contact plugs in the contact holes.

3 . The method of claim 2 , wherein the patterned hard mask comprises TiN.

4 . The method of claim 1 , further comprising:
forming an interlayer dielectric (ILD) layer around the gate structures, wherein the top surface of the ILD layer is even with the top surface of the first stop layer; forming a second dielectric layer on the first stop layer; forming a plurality of first contact plugs in the ILD layer and the second dielectric layer for electrically connecting to a source/drain region in the substrate; forming the second stop layer on the second dielectric layer and the first contact plugs; forming the first dielectric layer on the second stop layer; removing part of the first dielectric layer to form the first openings for exposing the second stop layer; removing part of the first dielectric layer, part of the second stop layer, and part of the second dielectric layer to form the second openings for exposing the first stop layer; removing part of the second stop layer and part of the first stop layer to expose the gate structures and the first contact plugs; and forming a plurality of second contact plugs for electrically connecting the first contact plugs and a plurality of third contact plugs for electrically connecting the gate structures.

5 . The method of claim 4 , wherein the first dielectric layer and the second dielectric layer comprise silicon oxide.

6 . The method of claim 4 , further comprising a fin-shaped structure on the substrate, wherein the fin-shaped structure is directly under the first contact plugs.

7 . The method of claim 6 , further comprising a shallow trench isolation (STI) around the fin-shaped structure, wherein the STI is directly under the third contact plugs.

8 . The method of claim 1 , wherein the first stop layer and the second stop layer comprise silicon nitride.

9 . The method of claim 1 , further comprising:
forming an interlayer dielectric (ILD) layer around the gate structures, wherein the top surface of the ILD layer is even with the top surface of the gate structures; forming the first stop layer on the gate structures and the ILD layer; forming a second dielectric layer on the first stop layer; forming a plurality of first contact plugs in the ILD layer and the second dielectric layer for electrically connecting to a source/drain region in the substrate; forming the second stop layer on the second dielectric layer and the first contact plugs; forming the first dielectric layer on the second stop layer; removing part of the first dielectric layer to form the first openings for exposing the second stop layer; removing part of the first dielectric layer, part of the second stop layer, and part of the second dielectric layer to form the second openings for exposing the first stop layer; removing part of the second stop layer and part of the first stop layer to expose the gate structures and the first contact plugs; and forming a plurality of second contact plugs for electrically connecting the first contact plugs and a plurality of third contact plugs for electrically connecting the gate structures.

10 . The method of claim 9 , wherein the first dielectric layer and the second dielectric layer comprise silicon oxide.

11 . The method of claim 9 , further comprising a fin-shaped structure on the substrate, wherein the fin-shaped structure is directly under the first contact plugs.

12 . The method of claim 9 , further comprising a shallow trench isolation (STI) around the fin-shaped structure, wherein the STI is directly under the third contact plugs.

13 . The method of claim 1 , wherein the gate structures comprise metal gates.

14 . A semiconductor device, comprising:
a substrate; a plurality of gate structures on the substrate; an interlayer dielectric (ILD) layer around the gate structures; a first etch stop layer on the ILD layer and the gate structures; a first dielectric layer on the first etch stop layer; a second etch stop layer on the first dielectric layer; a second dielectric layer on the second etch stop layer; a plurality of first contact plugs in the ILD layer, the first etch stop layer, and the first dielectric layer for electrically connecting to a source/drain region in the substrate; a plurality of second contact plugs in the second etch stop layer and the second dielectric layer for electrically connecting to the first contact plugs, wherein the top surfaces of the second contact plugs and the second dielectric layer are coplanar; and a plurality of third contact plugs in the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer for electrically connecting to the gate structures.

15 . The semiconductor device of claim 14 , wherein the gate structures comprise metal gates.

16 . The semiconductor device of claim 14 , wherein the first etch stop layer and the second etch stop layer comprise silicon nitride.

17 . The semiconductor device of claim 14 , wherein the first dielectric layer and the second dielectric layer comprise silicon oxide.

Assignees

• United Microelectronics Corp

Inventors

• Hung Ching-Wen
• Huang Chih-Sen
• Chen Yi-Wei
• Lin Chien-Ting
• Tzou Shih-Fang
• Lu Chia-Lin
• Chen Chun-Lung
• Liao Kun-Yuan
• Chang Feng-Yi
• Chen Chieh-Te

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D86/011

  comprising FinFETs · CPC title