Fully self-aligned interconnect structure

Patent metadata

Field	Value
Publication number	US-12136567-B2
Application number	US-202217838723-A
Country	US
Kind code	B2
Filing date	Jun 13, 2022
Priority date	Jun 8, 2020
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor substrate;
a first ILD layer disposed over the semiconductor substrate;
a patterned metal structure disposed in the first ILD layer, the patterned metal structure including a metal plug and a first metal feature, the patterned metal structure having a continuous sidewall slope from the metal plug to the first metal feature, and the patterned metal structure having a top surface;
a second metal feature directly contacting the top surface of the patterned metal structure; and
a first barrier layer on bottom and sidewall surfaces of the second metal feature.

2. The semiconductor structure of claim 1 , wherein a portion of the second metal feature adjacent the patterned metal structure includes a bottom surface that directly contacts the first barrier layer.

3. The semiconductor structure of claim 1 , wherein the patterned metal structure expands in width from top to bottom.

4. The semiconductor structure of claim 1 , wherein the patterned metal structure narrows in width from top to bottom.

5. The semiconductor structure of claim 1 , further comprising a second barrier layer disposed on sidewalls of the first metal feature.

6. The semiconductor structure of claim 5 , wherein
the first metal feature is longitudinally oriented along a first direction;
the metal plug includes first sidewalls spanned along the first direction and second sidewalls spanned along a second direction;
the first sidewalls of the metal plug directly contact the first ILD layer; and
the second sidewalls of the metal plug directly contact the second barrier layer and is separated from the first ILD layer by the second barrier layer.

7. The semiconductor structure of claim 6 , wherein the second barrier layer laterally encompasses and directly contacts the first metal feature.

8. The semiconductor structure of claim 7 , wherein the second barrier layer further extends to cover and contact a bottom surface of the first metal feature.

9. The semiconductor structure of claim 7 , further comprising a first etch stop layer (ESL) disposed underlying the first ILD layer, wherein the first ESL directly contacts the second barrier layer and the first ILD layer.

10. The semiconductor structure of claim 9 , wherein a bottom surface of the first barrier layer and a bottom surface of the first ESL are coplanar.

11. The semiconductor structure of claim 9 , further comprising a second ESL disposed on the first ILD layer, wherein the second ESL being extended to and aligned with edges of the patterned metal structure; and
the first barrier layer is extended to and aligned with edges of the second ESL.

12. A semiconductor structure, comprising:
a first ILD layer disposed over a substrate;
a patterned metal structure disposed in the first ILD layer, the patterned metal structure including a metal plug and a first metal layer having first metal lines, the patterned metal structure having a continuous sidewall slope from the metal plug to a first one of the first metal lines;
a second ILD layer disposed over the first ILD layer; and
a second metal layer disposed in the second ILD layer and including second metal lines, a first one of the second metal lines directly contacting a top surface of the metal plug.

13. The semiconductor structure of claim 12 , further comprising a first barrier layer on bottom and sidewall surfaces of the first metal lines.

14. The semiconductor structure of claim 13 , wherein
the first metal lines are longitudinally oriented along a first direction;
the metal plug includes first sidewalls spanned along the first direction and second sidewalls spanned along a second direction;
the first sidewalls of the metal plug directly contact the first ILD layer; and
the second sidewalls of the metal plug directly contact the first barrier layer and is separated from the first ILD layer by the first barrier layer.

15. The semiconductor structure of claim 13 , further comprising
a second barrier layer on bottom and sidewall surfaces of the second metal lines;
a first etch stop layer (ESL) disposed underlying the first ILD layer; and
a second ESL disposed on the first ILD layer, wherein the first ESL directly contacts the second barrier layer and the first ILD layer, wherein the second ESL directly contacts the first and second barrier layers.

16. The semiconductor structure of claim 15 , wherein
a bottom surface of the first barrier layer and a bottom surface of the first ESL are coplanar; and
a bottom the second barrier layer directly contacts a top surface of the second ESL.

17. The semiconductor structure of claim 16 , wherein
the second barrier layer extends to cover a bottom surface of a second one of the second metal lines; and
the second one of the second metal lines is separated from the first ILD layer by the second barrier layer and the second ESL.

18. A semiconductor structure, comprising:
a first ILD layer disposed over a substrate;
a patterned metal structure disposed in the first ILD layer, the patterned metal structure including a metal plug and a first metal layer having a first and second metal lines, the patterned metal structure having a continuous sidewall slope from the metal plug to the first metal line;
a second ILD layer disposed over the first ILD layer;
a second metal layer disposed in the second ILD layer and including a third and fourth metal lines, the third metal line directly contacting a top surface of the metal plug; and
a first barrier layer disposed in the first ILD layer, wherein the metal plug includes
a first sidewall directly contacting the first ILD layer, and
a second sidewall directly contacting the first barrier layer and being separated from the first ILD layer by the first barrier layer.

19. The semiconductor structure of claim 18 , further comprising
a second barrier layer disposed in the second ILD layer;
a first etch stop layer (ESL) disposed underlying the first ILD layer; and
a second ESL disposed overlying the first ILD layer, wherein a portion of the second barrier is interposed between the fourth metal line and the second ESL.

20. The semiconductor structure of claim 19 , wherein
the bottom surface of the third metal line vertically extends below a bottom surface of the second barrier layer; and
the fourth metal line include a bottom surface disposed on a top surface of the second barrier layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hsin-Ping
• Shue Shau-Lin
• Cao Min

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/264

  by chemical means · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title