Semiconductor wafer and method of manufacturing semiconductor apparatus

Patent metadata

Field	Value
Publication number	US-12131966-B2
Application number	US-202117467839-A
Country	US
Kind code	B2
Filing date	Sep 7, 2021
Priority date	Mar 20, 2019
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

A semiconductor wafer includes a surface having at least one recess including an inner wall surface. The inner wall surface is exposed.

First claim

What is claimed is:

1. A semiconductor wafer, comprising:
a surface having at least one recess including an inner wall surface and a bottom surface, the inner wall surface and the bottom surface being exposed, wherein:
the at least one recess includes a first recess and a second recess;
the first recess extends along a first direction of the surface;
the second recess extends along a second direction intersecting with the first direction on the surface;
each of the first and second recesses is surrounded by the corresponding inner wall surface; and
the surface further has a porous region.

2. The semiconductor wafer according to claim 1 , wherein
the at least one recess has a depth from the surface of 20 μm or more and an aspect ratio of 50 or more.

3. The semiconductor wafer according to claim 1 , wherein
a surface area of the surface is 50 times or more a surface area of a surface opposite to the surface.

4. The semiconductor wafer according to claim 1 , wherein
the at least one recess is provided via a partition.

5. The semiconductor wafer according to claim 1 , wherein
the surface further has a protrusion provided in the at least one recess.

6. The semiconductor wafer according to claim 1 , further comprising
a film provided on the surface.

7. The semiconductor wafer according to claim 6 , wherein
the film contains silicon carbide or silicon carbonitride.

8. The semiconductor wafer according to claim 1 , wherein
the semiconductor wafer is a silicon wafer, a silicon carbide wafer, a glass wafer, a quartz wafer, a sapphire wafer, or a compound semiconductor wafer.

9. The semiconductor wafer according to claim 1 , wherein
the semiconductor wafer is a silicon wafer.

10. The semiconductor wafer according to claim 1 , wherein
the semiconductor wafer consists of silicon.

11. The semiconductor wafer according to claim 1 , wherein
the inner wall surface and the bottom surface are exposed to an air.

Assignees

• Toshiba Kk
• Kioxia Corp

Inventors

• Ito Fuyuma
• Yoshimizu Yasuhito
• Kuge Nobuhito
• Kagi Yui
• Obata Susumu
• Matsuo Keiichiro
• Sano Mitsuo

Classifications

• H10P90/12

  Preparing bulk and homogeneous wafers · CPC title

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/27 Primary

  Structural arrangements therefor · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title