Temporary liquid thermal interface material for surface tension adhesion and thermal control
US-9269603-B2 · Feb 23, 2016 · US
Method of manufacturing semiconductor device
US2016233176A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016233176-A1 |
| Application number | US-201615009015-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jan 28, 2016 |
| Priority date | Feb 9, 2015 |
| Publication date | Aug 11, 2016 |
| Grant date | — |
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- Title
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Abstract
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A method for manufacturing a semiconductor device includes attaching a semiconductor substrate to a support substrate in a heated state, and processing the semiconductor substrate attached to the support substrate. The support substrate has a linear coefficient different from that of the semiconductor substrate. In an overlap region in which the support substrate overlaps the semiconductor substrate attached to the support substrate, a plurality of through-holes penetrating the support substrate from a front surface to a rear surface is provided. A straight line drawn on the front surface of the support substrate in any direction intersects with at least one of the through holes as long as the straight line is drawn through a center of the overlap region.
First claim
Opening claim text (preview).
1 . A method for manufacturing a semiconductor device, the method comprising: attaching a semiconductor substrate to a support substrate in a heated state; and processing the semiconductor substrate attached to the support substrate, wherein the support substrate has a linear expansion coefficient different from a linear expansion coefficient of the semiconductor substrate, in an overlap region in which the support substrate overlaps the semiconductor substrate attached to the support substrate, a plurality of through holes penetrate the support substrate from a front surface to a rear surface, and a straight line drawn through a center of the overlap region and on the front surface of the support substrate in any direction intersects with at least one of the through holes. 2 . The method of claim 1 , wherein the linear expansion coefficient of the support substrate is larger than the linear expansion coefficient of the semiconductor substrate. 3 . The method of claim 1 , wherein the plurality of through holes comprises: a group of first through holes extending intermittently along a first circle around the center of the overlap region; and a group of second through holes extending intermittently along a second circle around the center of the overlap region, and a radius of the first circle is different from a radius of the second circle. 4 . The method of claim 1 , wherein the plurality of through holes comprises: a group of third through holes extending along a first direction; and a group of fourth through holes extending along a second direction intersecting the first direction, and the third through holes and the fourth through holes are arranged in a matrix along the first and second directions so that each of the third through holes is adjacent to one of the fourth through holes and each of the fourth through holes is adjacent to one of the third through-holes.
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Classifications
Subject matter not provided for in other groups of this subclass · CPC title
- H10W42/121Primary
protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title
Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title
having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title
Anode regions of thyristors or collector regions of gated bipolar-mode devices · CPC title
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- What does patent US2016233176A1 cover?
- A method for manufacturing a semiconductor device includes attaching a semiconductor substrate to a support substrate in a heated state, and processing the semiconductor substrate attached to the support substrate. The support substrate has a linear coefficient different from that of the semiconductor substrate. In an overlap region in which the support substrate overlaps the semiconductor subs…
- Who is the assignee on this patent?
- Toyota Motor Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W42/121. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Aug 11 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).