Semiconductor devices having buried gates

Patent metadata

Field	Value
Publication number	US-12127394-B2
Application number	US-202318298230-A
Country	US
Kind code	B2
Filing date	Apr 10, 2023
Priority date	Sep 8, 2020
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including an active region; and
a gate structure in a gate trench in the substrate,
wherein the gate structure comprises:
a gate dielectric layer on a bottom surface and inner side surfaces of the gate trench;
a gate electrode layer on the gate dielectric layer in a lower portion of the gate trench, and including first, second, and third metal layers and a graphene layer contacting an upper surface of the first metal layer and contacting side surfaces of the second and third metal layers; and
a buried insulating layer on an upper surface of the gate electrode layer.

2. The semiconductor device of claim 1 , wherein an upper surface of the graphene layer is in contact with the buried insulating layer.

3. The semiconductor device of claim 1 , wherein an outer side surface of the graphene layer is in contact with the gate dielectric layer.

4. The semiconductor device of claim 1 , wherein the first and second metal layers have different work functions from each other.

5. The semiconductor device of claim 1 , wherein the graphene layer extends between an upper surface of the first metal layer and a lower surface of the second metal layer.

6. The semiconductor device of claim 1 , wherein the first and second metal layers have different widths from each other.

7. The semiconductor device of claim 6 , wherein the gate structure further comprises sidewall insulating layers on the gate dielectric layer on an upper surface of the first metal layer.

8. The semiconductor device of claim 6 , wherein an outer side surface of the first metal layer is in contact with the gate dielectric layer, and
wherein an outer side surface of the second metal layer is in contact with the graphene layer.

9. The semiconductor device of claim 1 , wherein the graphene layer has a smaller thickness than each of the first and second metal layers.

10. A semiconductor device, comprising:
a substrate including an active region having source/drain regions;
a gate electrode layer buried in the substrate, and including a plurality of metal layers overlapping each other in a direction perpendicular to an upper surface of the substrate, and a graphene layer at least partially covering a lower surface of any one of the plurality of metal layers, the graphene layer contacting side surfaces of at least two of the plurality of metal layers; and
a gate dielectric layer between the active region and the gate electrode layer.

11. The semiconductor device of claim 10 , wherein the graphene layer is interposed between at least portions of the plurality of metal layers.

12. The semiconductor device of claim 10 , wherein the plurality of metal layers have different work functions from each other.

13. The semiconductor device of claim 10 , wherein the plurality of metal layers include first and second metal layers sequentially stacked on the gate dielectric layer, and
wherein the graphene layer is interposed between the first and second metal layers.

14. The semiconductor device of claim 10 , wherein the plurality of metal layers include first and second metal layers sequentially stacked on the gate dielectric layer, and
wherein the graphene layer is interposed between the plurality of metal layers and the gate dielectric layer.

15. A semiconductor device, comprising:
a substrate including an active region;
a gate structure extending primarily in a first direction in a gate trench in the substrate;
a bit line extending primarily in a second direction, intersecting the first direction, on the substrate, the bit line being electrically connected to the active region on a first side of the gate structure; and
a capacitor on the bit line, and electrically connected to the active region on a second side of the gate structure,
wherein the gate structure comprises:
a gate dielectric layer on a bottom surface and inner side surfaces of the gate trench;
a first conductive layer on the gate dielectric layer, in a lower portion of the gate trench;
a second conductive layer on the first conductive layer;
a third conductive layer including graphene and is in contact with side surfaces of each of the first and second conductive layers; and
a buried insulating layer in an upper portion of the gate trench.

16. The semiconductor device of claim 15 , wherein the third conductive layer at least partially surrounds outer side surfaces and a lower surface of at least one of the first and second conductive layers.

17. The semiconductor device of claim 15 , wherein the third conductive layer at least partially covers a lower surface of any one of the first and second conductive layers.

18. The semiconductor device of claim 15 , wherein an upper surface of the third conductive layer is in contact with the buried insulating layer.

19. The semiconductor device of claim 15 , wherein an outer side surface of the third conductive layer is in contact with the gate dielectric layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Huijung
• Kwon Minwoo
• Han Sangyeon
• Kim Sangwon
• Kim Junsoo
• Shin Hyeonjin
• Lee Eunkyu

Classifications

• H10D64/01304

  characterised by the conductor · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title