Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2020105765-A1
Application number	US-201916564071-A
Country	US
Kind code	A1
Filing date	Sep 9, 2019
Priority date	Oct 2, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device comprises a substrate having a trench, a gate dielectric layer covering a surface of the trench, a gate electrode filling a lower portion of the trench, a capping pattern on the gate electrode in the trench, and a work function control pattern between the gate electrode and the capping pattern in the trench. The gate dielectric layer comprises a first segment having a first thickness between the gate electrode and the trench and a second segment having a second thickness between the capping pattern and the trench. The second thickness is less than the first thickness.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate having a trench; a gate dielectric layer covering a surface of the trench; a gate electrode filling a lower portion of the trench; a capping pattern on the gate electrode in the trench; and a work function control pattern between the gate electrode and the capping pattern in the trench, wherein the gate dielectric layer comprises:
a first segment provided between the gate electrode and the trench and having a first thickness; and
a second segment provided between the capping pattern and the trench and having a second thickness, the second thickness being less than the first thickness.

2 . The semiconductor device of claim 1 , wherein the gate dielectric layer further comprises:
a third segment provided between the work function control pattern and the trench and having a third thickness, wherein the third thickness is different from the first thickness and the second thickness.

3 . The semiconductor device of claim 2 , wherein the third thickness is less than the first thickness and equal to or greater than the second thickness.

4 . The semiconductor device of claim 3 ,
wherein the second thickness is 40% to 60% of the first thickness, and wherein the third thickness is 60% to 80% of the first thickness.

5 . The semiconductor device of claim 2 , further comprising:
a liner layer surrounding the work function control pattern in the trench, wherein a sum of a thickness of the liner layer and the third thickness is equal to the first thickness.

6 . The semiconductor device of claim 2 , wherein the third thickness is equal to the second thickness.

7 . The semiconductor device of claim 6 , wherein the second thickness is 60% to 80% of the first thickness.

8 . The semiconductor device of claim 1 , further comprising a barrier layer surrounding the gate electrode in the trench.

9 . The semiconductor device of claim 1 , wherein a work function of the work function control pattern is less than a work function of the gate electrode.

10 . The semiconductor device of claim 1 , wherein the work function control pattern comprises a material doped with N-type impurities.

11 . The semiconductor device of claim 1 ,
wherein the work function control pattern comprises polysilicon doped with N-type impurities, and wherein the gate electrode comprises one of Ta, Cu, W, and Ti.

12 . A method of fabricating a semiconductor device, the method comprising:
forming a trench in a substrate; forming a gate dielectric layer having a first thickness in the trench; sequentially forming on the gate dielectric layer a gate electrode, a work function control pattern, and a capping pattern, wherein the work function control pattern is formed between the gate electrode and the capping pattern; and controlling the gate dielectric layer to have various thicknesses at different portions of the gate dielectric layer, wherein controlling the gate dielectric layer to have the various thicknesses comprises: after forming the gate electrode and the work function control pattern in the trench, forming the gate dielectric layer to have a second thickness less than the first thickness, wherein the gate dielectric layer having the second thickness is exposed to a first exposure region in the trench.

13 . The method of claim 12 , wherein forming the gate dielectric layer to have the second thickness comprises selectively etching a portion of the gate dielectric layer exposed to the first exposure region.

14 . The method of claim 12 , wherein forming the gate dielectric layer to have the second thickness comprises:
removing the gate dielectric layer exposed to the first exposure region; and depositing a dielectric layer to have the second thickness in the trench of the first exposure region from which the gate dielectric layer is removed.

15 . The method of claim 12 , wherein controlling the gate dielectric layer to have the various thicknesses further comprises:
after forming the gate electrode in the trench, etching the gate dielectric layer to have a third thickness less than the first thickness, wherein the gate dielectric layer having the third thickness is exposed to a second exposure region in the trench.

16 . The method of claim 15 ,
wherein the second exposure region comprises the first exposure region, and wherein the second thickness is less than the third thickness.

17 . The method of claim 16 ,
wherein the second thickness is 40% to 60% of the first thickness, and wherein the third thickness is 60% to 80% of the first thickness.

18 . The method of claim 12 ,
wherein the work function control pattern comprises polysilicon doped with N-type impurities, and wherein the gate electrode comprises one of Ta, Cu, W, and Ti.

19 . A semiconductor device, comprising:
a device isolation layer that defines active regions of a substrate; and a gate line structure that intersects the active regions and is buried in a trench of the substrate, wherein the gate line structure comprises:
a gate electrode that fills a lower portion of the trench;
a work function control pattern on the gate electrode in the trench;
a capping pattern on the work function control pattern in the trench; and
a gate dielectric layer that extends along a surface of the trench and covers surfaces of the gate electrode, the work function control pattern, and the capping pattern,
wherein the gate dielectric layer comprises:
a first segment provided between the gate electrode and the trench and having a first thickness;
a second segment provided between the capping pattern and the trench and having a second thickness, the second thickness being less than the first thickness; and
a third segment provided between the work function control pattern and the trench and having a third thickness, the third thickness being greater than the second thickness.

20 . The semiconductor device of claim 19 ,
wherein the second thickness is 40% to 60% of the first thickness, and wherein the third thickness is 60% to 80% of the first thickness.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Keunnam
• Hwang Yoosang

Classifications

• H01L27/10823 Primary

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic

• H01L21/31111

  Electricity · mapped topic

• H01L27/10876

  Electricity · mapped topic

• H01L29/42368

  Electricity · mapped topic