Semiconductor device

Patent metadata

Field	Value
Publication number	US-12126344-B2
Application number	US-202118008287-A
Country	US
Kind code	B2
Filing date	Jul 12, 2021
Priority date	Jul 24, 2020
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

A semiconductor device with low power consumption can be provided. The semiconductor device includes a differential circuit and a latch circuit, the differential circuit includes a transistor including an oxide semiconductor in a channel formation region, and the latch circuit includes a transistor including a single semiconductor or a compound semiconductor in a channel formation region. The differential circuit and the latch circuit include an overlap region.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a differential circuit; and
a latch circuit,
wherein the differential circuit comprises a transistor including an oxide semiconductor in a channel formation region,
wherein the latch circuit comprises a transistor including silicon or gallium nitride in a channel formation region, and
wherein the differential circuit and the latch circuit comprise an overlap region.

2. A semiconductor device according to claim 1 ,
wherein the latch circuit comprises a transistor including an oxide semiconductor in a channel formation region.

3. A semiconductor device according to claim 1 ,
wherein the oxide semiconductor contains at least one of indium and zinc.

4. A semiconductor device comprising:
a differential circuit; and
a latch circuit,
wherein the differential circuit comprises first to fifth transistors,
wherein the latch circuit comprises sixth to twelfth transistors,
wherein each of the first to fifth transistors, the eleventh transistor, and the twelfth transistor comprises an oxide semiconductor in a channel formation region,
wherein each of the sixth to tenth transistors comprises silicon or gallium nitride in a channel formation region, and
wherein a first layer comprising the sixth to tenth transistors and a second layer comprising the first to fifth transistors, the eleventh transistor, and the twelfth transistor comprise an overlap region.

5. A semiconductor device according to claim 4 ,
wherein one of a source and a drain of the first transistor is electrically connected to a first terminal,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the first terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor are electrically connected to one of a source and a drain of the fifth transistor,
wherein a gate of the first transistor and a gate of the second transistor are electrically connected to a second terminal,
wherein a gate of the third transistor is electrically connected to a third terminal,
wherein a gate of the fourth transistor is electrically connected to a fourth terminal,
wherein a gate of the fifth transistor is electrically connected to a fifth terminal, and
wherein the other of the source and the drain of the fifth transistor is electrically connected to a sixth terminal.

6. A semiconductor device according to claim 5 ,
wherein one of a source and a drain of the sixth transistor is electrically connected to a seventh terminal,
wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to one of a source and a drain of the ninth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the sixth transistor is electrically connected to an eighth terminal,
wherein the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the tenth transistor,
wherein a gate of the seventh transistor and a gate of the ninth transistor is electrically connected to the one of the source and the drain of the tenth transistor,
wherein a gate of the eighth transistor and a gate of the tenth transistor is electrically connected to the one of the source and the drain of the ninth transistor,
wherein one of a source and a drain of the eleventh transistor is electrically connected to a ninth terminal and the one of the source and the drain of the ninth transistor,
wherein one of a source and a drain of the twelfth transistor is electrically connected to a tenth terminal and the one of the source and the drain of the tenth transistor,
wherein the other of the source and the drain of each of the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor is electrically connected to an eleventh terminal,
wherein a gate of the eleventh transistor is electrically connected to the one of the source and the drain of the third transistor, and
wherein a gate of the twelfth transistor is electrically connected to the one of the source and the drain of the fourth transistor.

7. A semiconductor device according to claim 4 ,
wherein the oxide semiconductor contains at least one of indium and zinc.

8. A semiconductor device comprising:
a differential circuit; and
a latch circuit,
wherein the differential circuit comprises first to fifth transistors,
wherein the latch circuit comprises sixth to twelfth transistors,
wherein each of the first to fifth transistors, the eleventh transistor, and the twelfth transistor comprises an oxide semiconductor in a channel formation region, and
wherein each of the sixth to tenth transistors comprises silicon or gallium nitride in a channel formation region.

9. A semiconductor device according to claim 8 ,
wherein one of a source and a drain of the first transistor is electrically connected to a first terminal,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the first terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor are electrically connected to one of a source and a drain of the fifth transistor,
wherein a gate of the first transistor and a gate of the second transistor are electrically connected to a second terminal,
wherein a gate of the third transistor is electrically connected to a third terminal,
wherein a gate of the fourth transistor is electrically connected to a fourth terminal,
wherein a gate of the fifth transistor is electrically connected to a fifth terminal, and
wherein the other of the source and the drain of the fifth transistor is electrically connected to a sixth terminal.

10. A semiconductor device according to claim 9 ,
wherein one of a source and a drain of the sixth transistor is electrically connected to a seventh terminal,
wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to one of a source and a drain of the ninth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the sixth transistor is electrically connected to an eighth terminal,
wherein the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the tenth transistor,
wherein a gate of the seventh transistor and a gate of the ninth transistor is electrically connected to the one of the source and the drain of the ten

Assignees

• Semiconductor Energy Lab

Inventors

• Hirose Takeya
• Yoneda Seiichi
• Negoro Yusuke

Classifications

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03K5/08

  by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) · CPC title

• H03K3/356104

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title