Semiconductor device

Patent metadata

Field	Value
Publication number	US-10224906-B2
Application number	US-201715438861-A
Country	US
Kind code	B2
Filing date	Feb 22, 2017
Priority date	Feb 25, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A hysteresis comparator that has a small circuit area and low power consumption is provided. A differential pair in the comparator is formed using transistors each including a back gate. The comparator is configured to apply an inverted signal of a logic value of an output signal of the comparator to the back gate of the transistor. That is, the threshold voltage of the transistor is controlled by the inverted signal. By the change of the threshold voltage, hysteresis can be added to an input comparison voltage.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a first circuit;
a second circuit;
a first inverter circuit;
a first constant current circuit; and
a second constant current circuit,
wherein the second transistor comprises a gate and a back gate,
wherein each of the first transistor and the second transistor is an n-channel transistor,
wherein the third transistor is a p-channel transistor,
wherein the first circuit has a first terminal, a second terminal, and a third terminal,
wherein the first circuit is configured to output a potential corresponding to current flowing through the first terminal and current flowing through the second terminal from the third terminal,
wherein the second circuit has a fourth terminal and a fifth terminal,
wherein the second circuit is configured to output one of two potentials from the fifth terminal in accordance with a potential applied to the fourth terminal,
wherein the first constant current circuit is configured to make constant current flow from an input terminal of the first constant current circuit to an output terminal of the first constant current circuit,
wherein the second constant current circuit is configured to make constant current flow from an input terminal of the second constant current circuit to an output terminal of the second constant current circuit,
wherein one of a source and a drain of the first transistor is electrically connected to the first terminal,
wherein the other of the source and the drain of the first transistor is electrically connected to the input terminal of the first constant current circuit,
wherein one of a source and a drain of the second transistor is electrically connected to the second terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to the input terminal of the first constant current circuit,
wherein a gate of the third transistor is electrically connected to the third terminal,
wherein one of a source and a drain of the third transistor is electrically connected to the input terminal of the second constant current circuit,
wherein an input terminal of the first inverter circuit is electrically connected to the one of the source and the drain of the third transistor,
wherein an output terminal of the first inverter circuit is electrically connected to the fourth terminal,
wherein the fifth terminal is electrically connected to the back gate of the second transistor,
wherein the first constant current circuit includes a sixth transistor,
wherein the second constant current circuit includes a seventh transistor,
wherein each of the sixth transistor and the seventh transistor is an n-channel transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the input terminal of the first constant current circuit,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the output terminal of the first constant current circuit,
wherein a gate of the sixth transistor is electrically connected to a gate of the seventh transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the input terminal of the second constant current circuit,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the output terminal of the second constant current circuit,
wherein each of the sixth transistor and the seventh transistor comprises a gate and a back gate,
wherein the back gate of the sixth transistor is electrically connected to the gate of the sixth transistor, and
wherein the back gate of the seventh transistor is electrically connected to the gate of the seventh transistor.

2. The semiconductor device according to claim 1 ,
wherein the first transistor has a back gate.

3. The semiconductor device according to claim 1 ,
wherein the second circuit includes a second inverter circuit,
wherein the second inverter circuit includes a fourth transistor,
wherein an input terminal of the second inverter circuit is electrically connected to the fourth terminal,
wherein an output terminal of the second inverter circuit is electrically connected to the fifth terminal, and
wherein a gate of the fourth transistor is electrically connected to the input terminal of the second inverter circuit.

4. The semiconductor device according to claim 1 ,
wherein the second circuit includes a fourth transistor and a first resistor,
wherein a gate of the fourth transistor is electrically connected to the fourth terminal,
wherein one of a source and a drain of the fourth transistor is electrically connected to one terminal of the first resistor, and
wherein the fifth terminal is electrically connected to the one of the source and the drain of the fourth transistor.

5. The semiconductor device according to claim 1 ,
wherein the second circuit includes a fourth transistor and a first diode,
wherein a gate of the fourth transistor is electrically connected to the fourth terminal,
wherein one of a source and a drain of the fourth transistor is electrically connected to an output terminal of the first diode, and
wherein the fifth terminal is electrically connected to the one of the source and the drain of the fourth transistor.

6. The semiconductor device according to claim 1 ,
wherein the first circuit includes a current mirror circuit,
wherein the current mirror circuit has a sixth terminal and a seventh terminal,
wherein the first terminal is electrically connected to the sixth terminal,
wherein the second terminal is electrically connected to the seventh terminal, and
wherein the third terminal is electrically connected to the seventh terminal.

7. The semiconductor device according to claim 1 ,
wherein the first circuit includes a second resistor and a third resistor,
wherein the first terminal is electrically connected to one terminal of the second resistor,
wherein the second terminal is electrically connected to one terminal of the third resistor, and
wherein the third terminal is electrically connected to the one terminal of the third resistor.

8. The semiconductor device according to claim 1 ,
wherein the first circuit includes a second diode and a third diode,
wherein the first terminal is electrically connected to an output terminal of the second diode,
wherein the second terminal is electrically connected to an output terminal of the third diode, and
wherein the third terminal is electrically connected to the output terminal of the third diode.

9. The semiconductor device according to claim 1 ,
wherein the first inverter circuit includes a fifth transistor, and
wherein a channel formation region of the fifth transistor includes an oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc.

10. The semiconductor device according to claim 1 ,
wherein a channel formation region of each of the first transistor and the second transistor includes an oxide containing at least one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin), and zinc.

11. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a first circuit;
a first inverter circuit;
a first constant current circuit; and
a second constant current circuit,
wherein the second transistor comprises a gate and a back gate,
wherein each of the first transistor and the second transistor is an n-channel transistor,
wherein the third transistor is a p-channel transistor,

Assignees

• Semiconductor Energy Lab

Inventors

• Yamamoto Roh

Classifications

• H03K3/02337 Primary

  Bistables with hysteresis, e.g. Schmitt trigger (non-regenerative amplitude discriminators G01R19/165) · CPC title

• H03K5/2481

  with at least one differential stage · CPC title

• H03K3/3565 Primary

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title