Comparator and semiconductor device including comparator

Patent metadata

Field	Value
Publication number	US-9935622-B2
Application number	US-201213451593-A
Country	US
Kind code	B2
Filing date	Apr 20, 2012
Priority date	Apr 28, 2011
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A chopper comparator with a novel structure is provided. The comparator includes an inverter, a capacitor, a first switch, a second switch, and a third switch. An input terminal and an output terminal of the inverter are electrically connected to each other through the first switch. The input terminal of the inverter is electrically connected to one of a pair of electrodes of the capacitor. A reference potential is applied to the other of the pair of electrodes of the capacitor through the second switch. A signal potential input is applied to the other of the pair of electrodes of the capacitor through the third switch. A potential output from the output terminal of the inverter is an output signal. A transistor whose channel is formed in an oxide semiconductor layer is used as the first switch.

First claim

What is claimed is:

1. A comparator comprising:
an inverter;
a capacitor;
a first switch;
a second switch; and
a third switch,
wherein an input terminal and an output terminal of the inverter are electrically connected to each other through the first switch,
wherein the first switch and the input terminal of the inverter are electrically connected to one of a pair of electrodes of the capacitor,
wherein the second switch and the third switch are electrically connected to the other of the pair of electrodes of the capacitor,
wherein the first switch comprises a first transistor whose channel is formed in an oxide semiconductor layer, and
wherein at least one of the second switch, the third switch, and the inverter comprises a second transistor whose channel is formed in a silicon layer or a silicon substrate.

2. The comparator according to claim 1 , wherein the first transistor overlaps with the second transistor.

3. The comparator according to claim 1 , wherein the oxide semiconductor layer comprises at least one of indium and zinc.

4. The comparator according to claim 1 , wherein the inverter is a clocked inverter configured to invert a signal input to an input terminal of the clocked inverter and outputs the inverted signal from an output terminal of the clocked inverter, in synchronization with a clock signal.

5. The comparator according to claim 1 ,
wherein a reference potential is applied to the other of the pair of electrodes of the capacitor when the second switch is in an on state,
wherein a signal potential is applied to the other of the pair of electrodes of the capacitor when the third switch is in an on state, and
wherein an output signal is output from the output terminal of the inverter.

6. The comparator according to claim 5 ,
wherein the second switch is electrically connected to a first terminal to which the reference potential is input, and
wherein the third switch is electrically connected to a second terminal to which the signal potential is input.

7. A semiconductor device comprising the comparator according to claim 1 .

8. A comparator comprising:
an inverter;
a capacitor;
a first switch;
a second switch; and
a third switch,
wherein an input terminal and an output terminal of the inverter are electrically connected to each other through the first switch,
wherein the first switch and the input terminal of the inverter are electrically connected to one of a pair of electrodes of the capacitor,
wherein the second switch and the third switch are electrically connected to the other of the pair of electrodes of the capacitor,
wherein the first switch comprises a plurality of transistors electrically connected in parallel to each other,
wherein each of channels of the plurality of transistors is formed in an oxide semiconductor layer, and
wherein at least one of the second switch, the third switch, and the inverter comprises a second transistor whose channel is formed in a silicon layer or a silicon substrate.

9. The comparator according to claim 8 , wherein the plurality of transistors are provided to overlap with each other.

10. The comparator according to claim 8 , wherein the first transistor overlaps with the second transistor.

11. The comparator according to claim 8 , wherein the oxide semiconductor layer comprises at least one of indium and zinc.

12. The comparator according to claim 8 , wherein the inverter is a clocked inverter configured to invert a signal input to an input terminal of the clocked inverter and outputs the inverted signal from an output terminal of the clocked inverter, in synchronization with a clock signal.

13. The comparator according to claim 8 ,
wherein a reference potential is applied to the other of the pair of electrodes of the capacitor when the second switch is in an on state,
wherein a signal potential is applied to the other of the pair of electrodes of the capacitor when the third switch is in an on state, and
wherein an output signal is output from the output terminal of the inverter.

14. The comparator according to claim 13 ,
wherein the second switch is electrically connected to a first terminal to which the reference potential is input, and
wherein the third switch is electrically connected to a second terminal to which the signal potential is input.

15. A semiconductor device comprising the comparator according to claim 8 .

16. A comparator comprising:
an inverter;
a capacitor;
a first switch;
a second switch; and
a third switch,
wherein an input terminal and an output terminal of the inverter are electrically connected to each other through the first switch,
wherein the first switch and the input terminal of the inverter are electrically connected to one of a pair of electrodes of the capacitor,
wherein the second switch and the third switch are electrically connected to the other of the pair of electrodes of the capacitor,
wherein the first switch comprises a plurality of transistors electrically connected in series with each other,
wherein each of channels of the plurality of transistors is formed in an oxide semiconductor layer, and
wherein at least one of the second switch, the third switch, and the inverter comprises a second transistor whose channel is formed in a silicon layer or a silicon substrate.

17. The comparator according to claim 16 , wherein the plurality of transistors are provided to overlap with each other.

18. The comparator according to claim 16 , wherein the first transistor overlaps with the second transistor.

19. The comparator according to claim 16 , wherein the oxide semiconductor layer comprises at least one of indium and zinc.

20. The comparator according to claim 16 , wherein the inverter is a clocked inverter configured to invert a signal input to an input terminal of the clocked inverter and outputs the inverted signal from an output terminal of the clocked inverter, in synchronization with a clock signal.

21. The comparator according to claim 16 ,
wherein a reference potential is applied to the other of the pair of electrodes of the capacitor when the second switch is in an on state,
wherein a signal potential is applied to the other of the pair of electrodes of the capacitor when the third switch is in an on state, and
wherein an output signal is output from the output terminal of the inverter.

22. The comparator according to claim 21 ,
wherein the second switch is electrically connected to a first terminal to which the reference potential is input, and
wherein the third switch is electrically connected to a second terminal to which the signal potential is input.

23. A semiconductor device comprising the comparator according to claim 16 .

Assignees

• Miyake Hiroyuki
• Semiconductor Energy Lab

Inventors

• Miyake Hiroyuki

Classifications

• H03K5/249

  using clock signals · CPC title

• H03K5/2472 Primary

  using field effect transistors (H03K5/2436 takes precedence) · CPC title