Apparatus with selectable majority gate and combinational logic gate outputs

Patent metadata

Field	Value
Publication number	US-12126339-B2
Application number	US-202218056243-A
Country	US
Kind code	B2
Filing date	Nov 16, 2022
Priority date	Dec 27, 2019
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.

First claim

We claim:

1. An apparatus comprising:
a first majority gate having a first set of inputs and a first output;
a reset mechanism coupled to the first majority gate;
a second majority gate having a second set of inputs and a second output; and
a selection circuitry to receive the first output and the second output, wherein the selection circuitry is to generate an output based, at least in part, on a control, and wherein the control is to cause the selection circuitry to select one of the first output or the second output as the output.

2. The apparatus of claim 1 , wherein the first majority gate includes ferroelectric material which is doped with Mn.

3. The apparatus of claim 1 , wherein the second majority gate includes ferroelectric material which is doped with Mn.

4. The apparatus of claim 1 , comprises a combinational logic having a third set of inputs and a third output, wherein the third output is received by the selection circuitry.

5. The apparatus of claim 1 , wherein the reset mechanism is a first reset mechanism, and wherein the apparatus comprises a second reset mechanism coupled to the second majority gate.

6. The apparatus of claim 1 , wherein the first majority gate includes non-linear polar material.

7. The apparatus of claim 6 , wherein the non-linear polar material includes one of a ferroelectric material, a paraelectric material, or a non-linear dielectric.

8. The apparatus of claim 1 , wherein the first majority gate includes:
a node to generate a majority function of the first set of inputs; and
a capacitor having a first terminal and a second terminal, wherein the first terminal is connected to the node, wherein the second terminal is connected to the first output, and wherein the capacitor includes non-linear polar material.

9. The apparatus of claim 8 , wherein the capacitor is a first capacitor, and wherein the apparatus comprises:
a second capacitor having a first terminal to receive a first input, and a second terminal coupled to the node;
a third capacitor having a first terminal to receive a second input, and a second terminal coupled to the node; and
a fourth capacitor having a first terminal to receive a third input, and a second terminal coupled to the node, wherein the first set of inputs includes the first input, the second input, and the third input.

10. The apparatus of claim 9 , wherein the second capacitor, the third capacitor, and the fourth capacitor comprise a ferroelectric material which is doped.

11. An apparatus comprising:
a majority gate having a first set of inputs and a first output, wherein the first output is operable to be reset, and wherein the majority gate includes a non-linear polar material;
a combinational logic gate having a second set of inputs and a second output; and
a selection circuitry to receive the first output and the second output, wherein the selection circuitry is to generate an output based, at least in part, on a control, and wherein the control is to cause the selection circuitry to select one of the first output or the second output as the output.

12. The apparatus of claim 11 , wherein the majority gate includes:
a node to generate a majority function of the first set of inputs; and
a capacitor having a first terminal and a second terminal, wherein the first terminal is connected to the node, and wherein the second terminal is connected to the first output, wherein the capacitor includes the non-linear polar material.

13. The apparatus of claim 12 , wherein the capacitor is a first capacitor, and wherein the apparatus comprises:
a second capacitor having a first terminal to receive a first input, and a second terminal coupled to the node;
a third capacitor having a first terminal to receive a second input, and a second terminal coupled to the node; and
a fourth capacitor having a first terminal to receive a third input, and a second terminal coupled to the node, wherein the first set of inputs includes the first input, the second input, and the third input.

14. The apparatus of claim 11 , wherein the majority gate includes ferroelectric material which is doped with Mn.

15. A system comprising:
a processor circuitry to execute one or more instructions;
a memory to store the one or more instructions; and
a communication interface coupled to the processor circuitry and the memory, wherein the processor circuitry includes:
a majority gate having a first set of inputs and a first output;
a combinational gate having a second set of inputs and a second output; and
a selection circuitry to receive the first output and the second output, wherein the selection circuitry is to generate an output based, at least in part, on a control, and wherein the control is to cause the selection circuitry to select one of the first output or the second output as the output.

16. The system of claim 15 , wherein the majority gate includes ferroelectric material which is doped with Mn.

17. The system of claim 15 , wherein the majority gate includes:
a node to generate a majority function of the first set of inputs; and
a capacitor having a first terminal and a second terminal, wherein the first terminal is connected to the node, and wherein the second terminal is connected to the first output, wherein the capacitor includes a non-linear polar material.

18. The system of claim 17 , wherein the capacitor is a first capacitor, and wherein the processor circuitry comprises:
a second capacitor having a first terminal to receive a first input, and a second terminal coupled to the node;
a third capacitor having a first terminal to receive a second input, and a second terminal coupled to the node; and
a fourth capacitor having a first terminal to receive a third input, and a second terminal coupled to the node, wherein the first set of inputs includes the first input, the second input, and the third input.

Assignees

• Kepler Computing Inc

Inventors

• Manipatruni Sasikanth
• Rios Rafael
• Odinaka Ikenna
• Menezes Robert
• Dokania Rajeev Kumar
• Ramesh Ramamoorthy
• Mathuriya Amrita

Classifications

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03K19/0008

  Arrangements for reducing power consumption · CPC title