Jitter cancellation with automatic performance adjustment

Patent metadata

Field	Value
Publication number	US-10164618-B1
Application number	US-201715857157-A
Country	US
Kind code	B1
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.

First claim

What is claimed is:

1. An apparatus, comprising:
a feedback loop configured to receive an input clock signal and output a delayed clock signal, the feedback loop comprising;
a first delay component configured to introduce, into a forward path of the feedback loop, a first delay that is inversely proportional to a supply voltage; and
a second delay component configured to introduce, into the forward path of the feedback loop, a second delay that is proportional to the supply voltage.

2. The apparatus of claim 1 , wherein the second delay component comprises:
a measurement circuit configured to determine an amount of jitter between the input clock signal and the delayed clock signal;
a control component configured to adjust a current level of a current source based at least in part on the amount of jitter; and
a cancellation circuit configured to introduce the second delay into the forward path of the feedback loop based at least in part on the current level of the current source and the supply voltage.

3. The apparatus of claim 2 , wherein responsiveness of the second delay component to a change in the supply voltage is inversely proportional to the current level of the current source.

4. The apparatus of claim 1 , wherein the second delay component comprises:
a bias circuit configured to generate a first bias voltage that is based at least in part on a digitally-controlled current level and is proportional to the supply voltage; and
a delay circuit configured to be biased by the first bias voltage and to introduce a delay into the forward path of the feedback loop that is directly proportional to the first bias voltage.

5. The apparatus of claim 1 , wherein the delayed clock signal comprises a data strobe signal for an output interface of a memory device.

6. The apparatus of claim 5 , wherein the output interface of the memory device is a double data rate (DDR) output interface.

7. An apparatus, comprising:
a bias circuit configured to generate a first bias voltage that is based at least in part on a current level of a current source and that is proportional to a supply voltage;
a delay circuit configured to receive an input clock signal and introduce a delay between the input clock signal and an output clock signal, the delay being proportional to the first bias voltage.

8. The apparatus of claim 7 , further comprising:
a second bias circuit configured to generate a second bias voltage that is inversely proportional to the supply voltage; and
wherein the delay introduced by the delay circuit is inversely proportional to the second bias voltage.

9. The apparatus of claim 7 , further comprising:
a state machine configured to control the current level of the current source based at least in part on determining, in order of decreasing significance, a desired value for each bit of a binary control number for the current source.

10. The apparatus of claim 9 , wherein determining the desired value of a bit of the binary control number comprises:
determining a first amount of jitter between the input clock signal and the output clock signal, the first amount of jitter associated with setting the bit to a high logic value and setting each less significant bit of the binary control number to a low logic value;
determining a second amount of jitter between the input clock signal and the output clock signal, the second amount of jitter associated with setting a least significant bit (LSB) of the binary control number to the high logic value; and
determining the desired value of the bit as the high logic value or the low logic value based at least in part determining the first amount of jitter and the second amount of jitter.

11. The apparatus of claim 10 , wherein determining the desired value of the bit as the high logic value or the low logic value comprises:
determining the desired value of the bit as the high logic value when the second amount of jitter is less than the first amount of jitter; and
determining the desired value of the bit as the low logic value when the second amount of jitter is greater than the first amount of jitter.

12. The apparatus of claim 7 , wherein the delay circuit comprises a plurality of inverters in series that are interposed between an input node that receives the input clock signal and an output node that outputs the output clock signal.

13. The apparatus of claim 12 , wherein each of the plurality of inverters comprises:
a first transistor configured as a pull-up transistor based at least in part on the first bias voltage; and
a second transistor configured as a pull-down transistor based at least in part on a second bias voltage.

14. The apparatus of claim 7 , wherein the delay comprises:
a first delay portion that is inversely proportional to the current level of the current source; and
a second delay portion that is proportional to the supply voltage.

15. The apparatus of claim 7 , wherein:
the input clock signal is associated with a reference clock for a memory device; and
the output clock signal is associated with a data strobe signal for the memory device.

16. A method, comprising:
determining a first amount of jitter between a first clock signal and a second clock signal, the first amount of jitter with a current source set to a first current level;
determining a second amount of jitter between the first clock signal and the second clock signal, the second amount of jitter with the current source set to a second current level;
comparing the first amount of jitter and the second amount of jitter;
determining a desired current level for the current source based at least in part on comparing the first amount of jitter and the second amount of jitter; and
setting the current source to the desired current level based at least in part on determining the desired current level.

17. The method of claim 16 , wherein
the current source is a digitally-controlled current source; and
setting the current source to a current level comprises setting a binary control number.

18. The method of claim 17 , further comprising:
setting the current source to the second current level by adjusting the binary control number by one.

19. The method of claim 17 , wherein determining the desired current level for the current source comprises:
determining, in order of decreasing significance, a desired value for each bit of the binary control number.

20. The method of claim 19 , wherein determining the desired value of a bit of the binary control number comprises:
determining an initial amount of jitter between the first clock signal and the second clock signal, the initial amount of jitter associated with setting the bit to a high logic value and each less significant bit of the binary control number to a low logic value;
determining a next amount of jitter between the first clock signal and the second clock signal, the next amount of jitter associated with setting a least significant bit (LSB) to the high logic value; and
determining the desired value of the bit as the high logic value or the low logic value based at least in part determining the initial amount of jitter and the next amount of jitter.

21. The method of claim 20 , wherein determining the desired value of the bit as the high logic value or the low logic value comprises:
determining the desired value of the bit as the high logic value when the next amount of jitter is less than the initial amount of jitter; and
determining the desired value of the bit as the low logic

Assignees

• Micron Technology Inc

Inventors

• Shi Dan
• Wei Fangxing
• Allen Michael J

Classifications

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F1/305

  in the event of power-supply fluctuations · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• H03K5/065 Primary

  using dispersive delay lines · CPC title

• H03K5/082

  with an adaptive threshold · CPC title