System on chip (SOC) with processor and integrated ferroelectric memory

Patent metadata

Field	Value
Publication number	US-12125513-B2
Application number	US-202217726864-A
Country	US
Kind code	B2
Filing date	Apr 22, 2022
Priority date	Apr 22, 2021
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.

First claim

What is claimed is:

1. A system on chip (SOC) integrated circuit device, comprising:
a processor circuit;
a ferroelectric memory formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer;
a read/write circuit configured to write data to the FMEs and to subsequently read back data from the FMEs responsive to respective write and read signals supplied by the processor circuit; and
a refresh circuit configured to selectively refresh the FMEs in a first mode and to not refresh the FMEs in a second mode responsive to a mode selection signal from the processor circuit, wherein the refresh circuit is further configured to receive an inhibit signal in the second mode and in response to receiving the inhibit signal disable the refresh the FMEs.

2. The SOC of claim 1 , wherein the refresh circuit refreshes the FMEs in the first mode by rewriting the data read back from the FMEs by the read/write circuit after a read operation directed by the processor circuit.

3. The SOC of claim 2 , wherein the read/write circuit transfers the read back data to a buffer memory, and wherein the refresh circuit transfers a copy of the read back data in the buffer memory to the FMEs.

4. The SOC of claim 1 , wherein the read back data from the FMEs recovered by the read/write circuit after a read operation are not returned to the FMEs.

5. The SOC of claim 1 , wherein the refresh circuit operates in the second mode to not refresh the FMEs responsive to a power down event detected by the processor circuit in which external electrical power is removed from the SOC.

6. The SOC of claim 1 , wherein the refresh circuit operates in the second mode to not refresh the FMEs responsive to use of a selected number of the FMEs as one-time programmable (OTP) memory elements to store security information that can only be read once from the OTP memory elements.

7. The SOC of claim 1 , wherein the refresh circuit operates in the second mode to not refresh the FMEs responsive to a detected security breach attack upon the SOC by the processor circuit.

8. The SOC of claim 1 , further comprising a buffer memory into which recovered readback data are stored responsive to a read operation by the read/write circuit upon the ferroelectric memory.

9. The SOC of claim 8 , wherein during the first mode the refresh circuit transfers a copy of the recovered readback data back to the ferroelectric memory, and wherein during the second mode the refresh circuit does not transfer a copy of the recovered readback data back to the ferroelectric memory.

10. The SOC of claim 1 , wherein the FMEs of the ferroelectric memory are arranged as ferroelectric field effect transistors (FeFETs).

11. A data storage device, comprising:
a non-volatile memory (NVM) arranged as a main store for user data;
a controller configured to perform data transfer operations to transfer the user data between the NVM and an external client; and
a local memory accessed by the controller during the data transfer operations, the local memory comprising an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer, the controller reading data stored in the FMEs and inhibiting a read-refresh operation thereon responsive to a selected condition, the controller and the local memory incorporated into a system on chip (SOC) integrated circuit device,
wherein the local memory further comprises a read/write circuit configured to write data to and read data from the FMEs and a refresh circuit configured to selectively refresh the data read from the FMEs by the read/write circuit responsive to a mode selection input signal supplied by the controller, wherein the refresh circuit is further configured to receive an inhibit signal in a second mode and in response to receiving the inhibit signal disable the refresh the FMEs.

12. The data storage device of claim 11 , wherein the controller is a programmable processor which operates responsive to firmware program instructions stored in a memory of the SOC integrated circuit device.

13. The data storage device of claim 11 , wherein the FMEs are characterized as a selected one of FeRAM, FeFET or FTJ ferroelectric memory cells.

14. The data storage device of claim 11 , wherein the FMEs normally operate in a first mode such that the FMEs are refreshed responsive to a read operation thereon during a normal operational mode of the data storage device, and wherein the FMEs operate in the second mode selected by the controller responsive to detection of an exception condition in which the FMEs are not refreshed responsive to a read operation thereon.

15. The data storage device of claim 14 , wherein the read back data from the FMEs recovered by the read/write circuit after a read operation are not returned to the FMEs.

16. The data storage device of claim 11 , further comprising inputting the inhibit signal into the refresh circuit in response to a power down operation.

17. The data storage device of claim 11 , further comprising inputting the inhibit signal into the refresh circuit in response to detection of an unauthorized third party attack on the data storage device.

18. The data storage device of claim 11 , further comprising inputting the inhibit signal into the refresh circuit in response to determining that a read operation on the FMEs is a destructive read operation.

Assignees

• Seagate Technology Llc

Inventors

• Trantham Jon D
• Viraraghavan Praveen
• Dykes John W
• Gilbert Ian J
• Kalarickal Sangita Shreedharan
• Totin Matthew J
• El-Batal Mohamad
• Mehta Darshana H

Classifications

• G11C11/2297

  Power supply circuits · CPC title

• G11C17/12

  using field-effect devices · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• H10B53/20

  characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title