Unipolar complementary logic

Patent metadata

Field	Value
Publication number	US-10153368-B2
Application number	US-201715656898-A
Country	US
Kind code	B2
Filing date	Jul 21, 2017
Priority date	Mar 1, 2017
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A system of unipolar digital logic. Ferroelectric field effect transistors having channels of a first polarity, are combined, in circuits, with simple field effect transistors having channels of the same polarity, to form logic gates and/or memory cells.

First claim

What is claimed is:

1. An integrated circuit comprising:
a plurality of field effect transistors, each of the field effect transistors of the integrated circuit having a channel of a first polarity, the plurality of field effect transistors comprising:
a first field effect transistor; and
a second field effect transistor,

the first field effect transistor being a simple field effect transistor, and the second field effect transistor being a ferroelectric field effect transistor,
wherein a source of the first field effect transistor is directly connected to a first power supply voltage, and
wherein a source of the second field effect transistor is directly connected to a second power supply voltage, greater than the first power supply voltage.

2. The integrated circuit of claim 1 , wherein the channel of the first polarity is an n-type channel.

3. The integrated circuit of claim 1 , wherein the channel of the first polarity is an n-type channel.

4. The integrated circuit of claim 1 , wherein the integrated circuit comprises a buffer-inverter comprising the first field effect transistor and the second field effect transistor.

5. The integrated circuit of claim 1 , wherein the integrated circuit comprises a logic gate configured to provide an AND function.

6. The integrated circuit of claim 5 , wherein the logic gate has:
a first input for a first input signal;
a second input for a second input signal;
a third input for an input signal that is a complement of the first input signal; and
a fourth input for an input signal that is a complement of the second input signal.

7. The integrated circuit of claim 5 , wherein the logic gate has:
a first output for a first output signal; and
a second output for an output signal that is a complement of the first output signal.

8. The integrated circuit of claim 5 , wherein the logic gate is further configured to provide an OR function.

9. The integrated circuit of claim 8 , wherein the logic gate is further configured to provide a NOR function.

10. The integrated circuit of claim 1 , wherein the integrated circuit comprises a logic gate configured to provide an AND-OR-invert function.

11. The integrated circuit of claim 10 , wherein the logic gate is further configured to provide an OR-AND-invert function.

12. The integrated circuit of claim 1 , wherein the integrated circuit comprises a memory cell configured to provide a static random access memory cell function.

13. The integrated circuit of claim 1 , wherein the integrated circuit comprises a memory cell configured to provide a data flip-flop function.

14. A circuit comprising a logic gate configured to operate as an AND gate, the circuit having:
a first input;
a second input;
a third input;
a fourth input; and
a first output
the circuit comprising:
a first simple field effect transistor having a channel of a first polarity, and a source directly connected to a first power supply voltage and a drain;
a second simple field effect transistor having a source connected to the drain of the first simple field effect transistor and a drain connected to the first output;
a first ferroelectric field effect transistor having a channel of the first polarity, and a source directly connected to a second power supply voltage, greater than the first power supply voltage, and a drain connected to the first output; and
a second ferroelectric field effect transistor having a source connected to the second power supply voltage and a drain connected to the first output.

15. The circuit of claim 14 , wherein the logic gate is further configured to operate as a NAND gate.

16. The circuit of claim 15 , wherein the logic gate is further configured to operate as an OR gate.

17. The circuit of claim 16 , wherein the logic gate is further configured to operate as a NOR gate.

18. The circuit of claim 15 , further having a second output, the second output being configured to operate as a complementary AND output or as an output of the NAND gate, the circuit further comprising:
a third simple field effect transistor having a source connected to the first power supply voltage and a drain connected to the second output;
a fourth simple field effect transistor having a source connected to the first power supply voltage and a drain connected to the second output;
a third ferroelectric field effect transistor having a source connected to a second power supply voltage, greater than the first power supply voltage, and a drain; and
a fourth ferroelectric field effect transistor having a source connected to the drain of the third ferroelectric field effect transistor and a drain connected to the second output.

19. An integrated circuit comprising:
a plurality of field effect transistors, each of the field effect transistors of the integrated circuit having a channel of a first polarity, the plurality of field effect transistors comprising:
a first field effect transistor; and
a second field effect transistor,

the first field effect transistor being a simple field effect transistor, and the second field effect transistor being a ferroelectric field effect transistor,
wherein the integrated circuit comprises:
a logic gate configured to provide an AND function; and
a memory cell configured to provide a data flip-flop function,

wherein a source of the first field effect transistor is directly connected to a first power supply voltage, and
wherein a source of the second field effect transistor is directly connected to a second power supply voltage, greater than the first power supply voltage.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hatcher Ryan M
• Sengupta Rwik
• Bowen Chris

Classifications

• H01L27/1104

  Electricity · mapped topic

• H01L29/78391 Primary

  Electricity · mapped topic

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H10D30/701 Primary

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D89/00 Primary

  Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00 · CPC title