Display device and electronic device

Patent metadata

Field	Value
Publication number	US-12119410-B2
Application number	US-201916599296-A
Country	US
Kind code	B2
Filing date	Oct 11, 2019
Priority date	Oct 19, 2018
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

A display device in which a plurality of pixels are arranged in an array is provided. Each of the plurality of pixels comprises a current path that includes a light emitting element and a first transistor, and a second transistor for transmitting a luminance signal. The first transistor comprises diffusion regions arranged in the current path, and a gate electrode to which the luminance signal is transmitted from the second transistor. The diffusion regions are of a first conductivity type, and the gate electrode is of a second conductivity type opposite to the first conductivity type.

First claim

What is claimed is:

1. A display device comprising:
a silicon substrate; and
a plurality of pixels arranged in an array,
wherein each of the plurality of pixels comprises: a current path that includes a light emitting element and a first transistor; a second transistor for transmitting a luminance signal; and a reset transistor for shorting between terminals of the light emitting element,
wherein the first transistor comprises (1) diffusion regions arranged in the current path, (2) a channel region arranged between the diffusion regions, and (3) a gate electrode to which the luminance signal is transmitted from the second transistor,
wherein the diffusion regions of the first transistor are of a first conductivity type,
wherein the gate electrode of the first transistor is of a second conductivity type opposite to the first conductivity type,
wherein the diffusion regions of the first transistor are provided in a well of the silicon substrate, the well having the second conductivity type,
wherein diffusion regions of the reset transistor are of the first conductivity type,
wherein a gate electrode of the reset transistor is of the first conductivity type,
wherein the reset transistor is connected to an anode of the light emitting element,
wherein the reset transistor is switchable between a conductive state and a non-conductive state, and
wherein, by the reset transistor entering the conductive state, the terminals of the light emitting element are shorted and the light emitting element is in a non-light-emitting state.

2. The display device according to claim 1 , wherein an impurity concentration of a channel region of the first transistor is lower than an impurity concentration of a channel region of the second transistor.

3. The display device according to claim 1 , wherein a channel region of the first transistor is of the first conductivity type.

4. The display device according to claim 3 , wherein an impurity of the diffusion regions is higher than an impurity of the channel region of the first transistor.

5. The display device according to claim 1 , wherein the first transistor and the second transistor are arranged in the well, and
wherein an impurity concentration of a channel region of the first transistor is lower than an impurity concentration of the well.

6. The display device according to claim 5 , wherein each of the plurality of pixels further comprises a fourth transistor that is arranged in the current path, the fourth transistor being configured for controlling a conductive state of the current path,
wherein diffusion regions of the fourth transistor are of the first conductivity type,
wherein a gate electrode of the fourth transistor is of the second conductivity type, and
wherein the impurity concentration of the channel region of the fourth transistor is lower than the impurity concentration of the well.

7. The display device according to claim 1 , wherein each of the plurality of pixels further comprises a fourth transistor that is arranged in the current path, the fourth transistor being configured for controlling a conductive state of the current path.

8. The display device according to claim 7 , wherein diffusion regions of the fourth transistor are of the first conductivity type, and
wherein a gate electrode of the fourth transistor is of the second conductivity type.

9. The display device according to claim 7 , wherein an impurity concentration of a channel region of the fourth transistor is lower than an impurity concentration of a channel region of the second transistor.

10. The display device according to claim 7 , wherein a channel region of the fourth transistor is of the first conductivity type.

11. The display device according to claim 7 , wherein an impurity concentration of the gate electrode of the first transistor and an impurity concentration of a gate electrode of the fourth transistor are different from each other.

12. The display device according to claim 7 , wherein the first transistor is arranged between the light emitting element and the fourth transistor.

13. The display device according to claim 7 , wherein an impurity concentration of a channel region of the fourth transistor is lower than an impurity concentration of a channel region of the reset transistor.

14. The display device according to claim 1 , wherein an impurity concentration of a channel region of the first transistor is lower than an impurity concentration of a channel region of the reset transistor.

15. The display device according to claim 1 , wherein a channel region of the reset transistor is of the first conductivity type.

16. The display device according to claim 1 , wherein diffusion regions and a gate electrode of the second transistor are of the first conductivity type, and
wherein a channel region of the second transistor is of the second conductivity type.

17. An electronic device comprising:
the display device according to claim 1 ; and
a control unit configured to control driving of the display device.

18. The display device according to claim 1 , wherein the gate electrode of the first transistor is a semiconductor of a same conductivity type as the substrate.

19. The display device according to claim 1 , wherein the substrate is composed of a semiconductor.

20. The display device according to claim 19 , wherein an insulation layer is arranged between the channel region and the gate electrode, and
wherein the insulation layer is composed of an oxide of the semiconductor.

Assignees

• Canon Kk

Inventors

• Tsuboi Hiromasa

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10B20/30

  having the source region and the drain region on the same level, e.g. lateral transistors · CPC title