Semiconductor package

Patent metadata

Field	Value
Publication number	US-12119305-B2
Application number	US-202318161066-A
Country	US
Kind code	B2
Filing date	Jan 29, 2023
Priority date	Aug 25, 2020
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip electrically connected to the first redistribution layer; a vertical connection structure adjacent a periphery of the semiconductor chip and electrically connected to the first redistribution layer; and an encapsulant on the vertical connection structure. The vertical connection structure includes a metal pillar having a bottom surface facing the redistribution substrate, a top surface positioned opposite to the bottom surface, and a side surface positioned between the bottom surface and the top surface. The vertical connection structure further includes a plating layer on each of the bottom surface, the top surface, and the side surface of the metal pillar, and having a roughened surface.

First claim

What is claimed is:

1. A semiconductor package comprising:
a redistribution substrate comprising a first redistribution layer;
a semiconductor chip on the redistribution substrate and electrically connected to the first redistribution layer;
at least one vertical connection structure adjacent the semiconductor chip and having a first surface roughness;
a core structure on the redistribution substrate and having a first through-hole in which the semiconductor chip is disposed, at least one second through-hole in which the at least one vertical connection structure is disposed, and a second surface roughness;
an encapsulant on the redistribution substrate, the semiconductor chip, the core structure, and the at least one vertical connection structure; and
a redistribution structure on the encapsulant and comprising a second redistribution layer,
wherein the at least one vertical connection structure is electrically connected to the first redistribution layer at a bottom surface thereof and the second redistribution layer at a top surface thereof, and
the core structure is electrically insulated to the first redistribution layer and the second redistribution layer.

2. The semiconductor package as claimed in claim 1 , wherein the first surface roughness and the second surface roughness are about 0.5 μm or more.

3. The semiconductor package as claimed in claim 1 , wherein the core structure surrounds side surfaces of each of the semiconductor chip and the at least one vertical connection structure.

4. The semiconductor package as claimed in claim 1 , wherein the at least one vertical connection structure and the core structure comprise a same material.

5. The semiconductor package as claimed in claim 1 , wherein respective portions of the encapsulant substantially fill a first space between the first through-hole and the semiconductor chip, and a second space between the at least one second through-hole and the at least one vertical connection structure.

6. The semiconductor package as claimed in claim 1 , wherein the core structure is electrically insulated from the vertical connection structure.

7. The semiconductor package as claimed in claim 1 , wherein the at least one vertical connection structure comprises a metal pillar extending in a vertical direction and a first plating layer on a surface of the metal pillar, and
the first plating layer provides the first surface roughness.

8. The semiconductor package as claimed in claim 1 , wherein the core structure comprises a metal frame including the first through-hole and the at least one second through-hole extending therethrough, and a second plating layer on a surface of the metal frame, and
the second plating layer provides the second surface roughness.

9. The semiconductor package as claimed in claim 1 , wherein the redistribution substrate further comprises a first redistribution via extending from the first redistribution layer to the bottom surface of the vertical connection structure.

10. The semiconductor package as claimed in claim 9 , wherein the first redistribution via is in contact with the bottom surface of the vertical connection structure.

11. The semiconductor package as claimed in claim 1 , wherein the redistribution structure further comprises a second redistribution via extending from the second redistribution layer to the top surface of the vertical connection structure.

12. The semiconductor package as claimed in claim 11 , wherein the second redistribution via is in contact with the top surface of the vertical connection structure.

13. A semiconductor package comprising:
a first redistribution structure comprising a first redistribution layer;
a semiconductor chip on the first redistribution structure and electrically connected to the first redistribution layer;
an encapsulant on the first redistribution structure, and the semiconductor chip;
a second redistribution structure on the encapsulant and comprising a second redistribution layer electrically connected to the first redistribution layer;
a plurality of through vias penetrating through the encapsulant and electrically connected to the first redistribution layer and the second redistribution layer; and
a plurality of connection bumps below the first redistribution structure and electrically connected to the first redistribution layer,
wherein each of the plurality of through vias has a bottom surface, a top surface, and a side surface, on which a surface roughness is formed, respectively, and
wherein each of the plurality of through vias is connected to the first redistribution layer at the bottom surface thereof and the second redistribution layer at the top surface thereof.

14. The semiconductor package as claimed in claim 13 , wherein the plurality of through vias comprises a metal pillar extending between the first redistribution structure and the second redistribution structure in a vertical direction, and a plating layer covering all surfaces of the metal pillar, and
wherein the plating layer defines the bottom surface, the top surface, and the side surface of the plurality of through vias.

15. The semiconductor package as claimed in claim 13 , wherein the first redistribution structure further comprises a first insulating layer between the first redistribution layer and the plurality of through vias, and a first redistribution via extending through the first insulating layer and contacting the bottom surface of the plurality of through vias.

16. The semiconductor package as claimed in claim 13 , wherein the second redistribution structure further comprises a second insulating layer between the second redistribution layer and the encapsulant covering the top surface of each of the plurality of through vias, and a second redistribution via extends through the second insulating layer and a part of the encapsulant to covering the top surface of each of the plurality of through vias, and
the second redistribution via is in contact with the top surface of the plurality of through vias.

17. The semiconductor package as claimed in claim 13 , wherein the encapsulant comprises an opening on the top surface of each of the plurality of through vias,
the second redistribution structure further comprises a second insulating layer between the second redistribution layer and the encapsulant, and extending into the opening of the encapsulant, and a second redistribution via extending through the second insulating layer in the opening, and
the second redistribution via is in contact with the top surface of the plurality of through vias.

18. A semiconductor package comprising:
a semiconductor chip comprising a connection pad;
at least one vertical connection structure adjacent the semiconductor chip and having a surface roughness; and
a redistribution substrate below the semiconductor chip and the at least one vertical connection structure and comprising a first insulating layer, a first redistribution layer below the first insulating layer, and a first redistribution via electrically connecting the first redistribution layer to the connection pad and the at least one vertical connection structure,
wherein the first redistribution via is in contact with a bottom surface of the at least one vertical connection structure through the first insulating layer, and
the bottom surface of the at least one vertical connection structure has the surface roughness.

19. The semiconductor package as claimed in claim 18 , further comprising a redistribution structure on the semiconductor chip and the at lea

Assignees

• Samsung Electronics Co Ltd

Inventors

• Mun Kyungdon
• Kang Myungsam
• Ko Youngchan
• Kwon Yieok
• Kim Jeongseok
• Lee Gongje
• Cho Bongju

Classifications

• H10W70/6525

  for securing the interconnections to the substrate, e.g. to prevent peeling · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title