Semiconductor package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10020263-B2
Application number	US-201615297365-A
Country	US
Kind code	B2
Filing date	Oct 19, 2016
Priority date	Apr 7, 2016
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

Provided are a semiconductor package and a manufacturing method thereof for securing a space for mounting a semiconductor device by etching a temporary metal plate to form a plurality of conductive posts.

First claim

What is claimed:

1. A method of manufacturing a semiconductor package, the method comprising:
forming conductive posts by etching a metal plate, wherein after said etching, the conductive posts are connected to a remaining planar portion of the metal plate;
filling between the conductive posts with a filler;
removing the remaining planar portion of the metal plate;
forming first conductive patterns on a top surface of the filler and on top surfaces of the conductive posts, wherein one or more of the first conductive patterns are electrically connected to corresponding one or more of the conductive posts;
forming a dielectric layer that covers the filler, the conductive posts, and the first conductive patterns;
forming conductive vias that extend through the dielectric layer and connect to the first conductive patterns;
forming second conductive patterns on a top surface of the dielectric layer, wherein the second conductive patterns are electrically connected to the conductive vias; and
at least one of:
mounting a first semiconductor die on a top surface of the dielectric layer to electrically connect the first semiconductor die to at least a portion of the second conductive patterns; or
mounting a second semiconductor die on a bottom surface of the dielectric layer to electrically connect the second semiconductor die to at least a portion of the first conductive patterns.

2. The method of claim 1 , wherein the second semiconductor die is mounted on the bottom surface of the dielectric layer to electrically connect the second semiconductor die to the at least a portion of the first conductive patterns.

3. The method of claim 1 , wherein the first semiconductor die is mounted on the top surface of the dielectric layer to electrically connect the first semiconductor die to the at least a portion of the second conductive patterns.

4. The method of claim 1 , wherein a height between top and bottom surfaces of each of the conductive posts ranges from substantially 60 μm to substantially 100 μm.

5. The method of claim 1 , wherein a distance between adjacent ones of the conductive posts ranges from substantially 90 μm to substantially 500 μm.

6. The method of claim 1 , wherein a width of each of the conductive posts ranges from substantially 200 μm to substantially 450 μm.

7. The method of claim 1 , comprising removing the filler to expose a portion of the first conductive patterns, side surfaces of the conductive posts, and a portion of the first dielectric layer.

8. The method of claim 7 , comprising covering the exposed portion of the first conductive patterns, the exposed side surfaces of the conductive posts, the exposed portion of the first dielectric layer, and a portion of the second semiconductor die with an encapsulating material.

9. The method of claim 1 , comprising covering at least a portion of the first semiconductor die in a first encapsulating material.

10. The method of claim 9 , comprising covering at least a portion of the second semiconductor die in a second encapsulating material separate from the first encapsulating material.

11. A method for manufacturing a semiconductor package, the method comprising:
forming conductive posts from a metal plate, wherein the conductive posts are joined at their bottom portions by a portion of the metal plate;
surrounding the conductive posts with an insulating layer;
removing the portion of the metal plate;
forming first conductive patterns on the insulating layer and the conductive posts to electrically connect at least a portion of the first conductive patterns to a corresponding one of each of the conductive posts;
forming a dielectric layer over the first conductive patterns, the insulating layer, and the conductive posts;
forming conductive vias through the dielectric layer to electrically connect to at least a portion of the first conductive patterns;
forming second conductive patterns on the dielectric layer and the conductive vias to electrically connect at least a portion of the second conductive patterns to a corresponding one of each of the conductive vias;
removing the insulating layer to expose at least a portion of the dielectric layer and at least a portion of the first conductive patterns;
mounting at least one semiconductor device to one or both of a top surface of the dielectric layer and a bottom surface of the dielectric layer; and
covering entirely, with an encapsulant, the at least one semiconductor device.

12. The method according to claim 11 , wherein mounting the at least one semiconductor device includes mounting a semiconductor device on the bottom surface of the dielectric layer to couple the semiconductor device to at least a part of the first conductive patterns.

13. The method according to claim 11 , wherein mounting the at least one semiconductor device includes mounting a semiconductor device on the top surface of the dielectric layer to couple the semiconductor device to at least a part of the second conductive patterns.

14. The method according to claim 11 , wherein a height between top and bottom surfaces of each of the conductive posts ranges from substantially 60 μm to substantially 100 μm.

15. The method according to claim 11 , wherein a distance between adjacent ones of the conductive posts ranges from substantially 90 μm to substantially 500 μm.

16. The method according to claim 11 , wherein a width of each of the conductive posts ranges from substantially 200 μm to substantially 450 μm.

17. The method according to claim 11 , wherein mounting the at least one semiconductor device includes:
mounting a first semiconductor device on the top surface of the dielectric layer to be electrically connected to the second conductive patterns, and
mounting a second semiconductor device on the bottom surface of the dielectric layer to be electrically connected to the first conductive patterns.

18. The method according to claim 17 , comprising electrically connecting a plurality of conductive bumps to bottom surfaces of the conductive posts.

19. The method according to claim 17 , comprising:
electrically connecting the second semiconductor device to the first conductive patterns in a central region of the bottom surface of the dielectric layer; and
electrically connecting the conductive posts to the first conductive patterns in a peripheral region of the bottom surface of the dielectric layer.

20. The method according to claim 19 , wherein covering entirely, with the encapsulant, comprises:
covering, with a first encapsulant, at least the first semiconductor device and the top surface of the dielectric layer; and
covering, with a second encapsulant, at least the second semiconductor device and the bottom surface of the dielectric layer while leaving exposed bottom surfaces of the conductive posts to the outside.

Assignees

• Amkor Technology Inc

Inventors

• Lee Kyoung Yeon
• Lee Tae Yong
• Shin Min Chul
• Oh Se Man

Classifications

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title