Integrated circuit device

Patent metadata

Field	Value
Publication number	US-12113108-B2
Application number	US-202117472926-A
Country	US
Kind code	B2
Filing date	Sep 13, 2021
Priority date	Feb 4, 2021
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a fin-type active region extending along a first horizontal direction on a substrate;
a plurality of gate structures each comprising a gate line extending along a second horizontal direction crossing the first horizontal direction on the fin-type active region and insulation spacers on sidewalls of the gate line;
a source/drain contact between a first gate structure and a second gate structure, which are among the gate structures and are adjacent to each other, and having opposing sides that are asymmetric in the first horizontal direction; and
an insulation liner on sidewalls of the source/drain contact,
wherein the source/drain contact comprises a lower contact portion facing the first gate structure and the second gate structure in the first horizontal direction and an upper contact portion that is integral to the lower contact portion, the upper contact portion comprises a horizontal extension, which extends on an upper corner of the first gate structure adjacent to the source/drain contact and overlaps at least a portion of the first gate structure in a vertical direction,
wherein the insulation liner comprises a first local region that electrically separates the upper corner of the first gate structure and the horizontal extension of the source/drain contact, and a second local region that is farther from the substrate than the first local region, and
wherein a thickness of the first local region is greater than that of the second local region.

2. The integrated circuit device of claim 1 , wherein the first gate structure comprises a first gate line and a first insulation spacer between the first gate line and the source/drain contact, the first insulation spacer having a top portion defining a portion of the upper corner of the first gate structure,
the second gate structure comprises a second gate line and a second insulation spacer between the second gate line and the source/drain contact, and
at least a portion of the top portion of the first insulation spacer is closer to the substrate than a topmost surface of the second insulation spacer, and the first local region of the insulation liner is between the top portion and the source/drain contact.

3. The integrated circuit device of claim 1 , wherein, in the first horizontal direction, a width of the upper contact portion of the source/drain contact is greater than a width of the lower contact portion.

4. The integrated circuit device of claim 1 , wherein, in the first horizontal direction, a distance between the source/drain contact and the first gate structure is less than a distance between the source/drain contact and the second gate structure.

5. The integrated circuit device of claim 1 , wherein the insulation liner further comprises a third local region that is closer to the substrate than the first local region, and the thickness of the first local region is greater than that of the third local region.

6. The integrated circuit device of claim 1 , wherein the insulation liner comprises a first insulation liner including a portion in contact with the upper corner of the first gate structure and a second insulation liner stacked on the first insulation liner and including a portion in contact with the horizontal extension of the source/drain contact,
the first insulation liner has a same thickness in the first local region and the second local region, and
a thickness of the second insulation liner in the first local region is greater than a thickness of the second insulation liner in the second local region.

7. The integrated circuit device of claim 1 , further comprising an inter-gate insulation layer between the second gate structure and the insulation liner,
wherein the first gate structure is in contact with the insulation liner in the first horizontal direction, and
the second gate structure is spaced apart from the insulation liner in the first horizontal direction with the inter-gate insulation layer therebetween.

8. The integrated circuit device of claim 1 , wherein the source/drain contact is in a source/drain contact hole, and wherein the insulation liner comprises:
a first insulation liner on an inner wall of the source/drain contact hole between the first gate structure and the second gate structure; and
a second insulation liner between the first insulation liner and the source/drain contact and in contact with the source/drain contact,
the first insulation liner has a uniform thickness within the source/drain contact hole, and
the second insulation liner has a non-uniform thickness within the source/drain contact hole that is largest in the first local region.

9. The integrated circuit device of claim 6 , wherein the first insulation liner comprises a first silicon nitride film, and the second insulation liner comprises a second silicon nitride film having a different density than the first silicon nitride film.

10. The integrated circuit device of claim 1 , further comprising:
a source/drain region on the fin-type active region between the first gate structure and the second gate structure; and
a metal silicide layer between the source/drain region and the source/drain contact, the metal silicide layer having a bottom surface in contact with the source/drain region and a top surface in contact with the source/drain contact,
wherein, in the first horizontal direction, a distance from the metal silicide layer to the first gate structure is less than a distance from the metal silicide layer to the second gate structure.

11. An integrated circuit device comprising:
a fin-type active region extending along a first horizontal direction on a substrate;
a plurality of gate structures extending along a second horizontal direction crossing the first horizontal direction on the fin-type active regions;
a source/drain region on the fin-type active region between a pair of gate structures among the gate structures, wherein the pair of gate structures are adjacent to each other;
a source/drain contact that extends along a vertical direction on the source/drain region and has opposing sides in the first horizontal direction that are asymmetric; and
an insulation liner on sidewalls of the source/drain contact,
wherein the source/drain contact comprises a lower contact portion facing the pair of gate structures in the first horizontal direction and an upper contact portion that is integral to the lower contact portion, the upper contact portion comprises a horizontal extension, which extends on an upper corner of a first gate structure of the pair of gate structures and overlaps at least a portion of the first gate structure in the vertical direction,
wherein the insulation liner comprises a first local region that electrically separates the upper corner of the first gate structure and the horizontal extension of the source/drain contact, and a second local region that is farther from the substrate than the first local region, and
wherein a thickness of the first local region is greater than that of the second local region.

12. The integrated circuit device of claim 11 , wherein opposing sides of the first gate structure are asymmetric in the first horizontal direction.

13. The integrated circuit device of claim 11 , wherein the gate structures each comprise a gate line, an insulation capping line on a top surface of the gate line, and insulation spacers on sidewalls of the gate line and the insulation capping line,
wherein the insulation spacer of the first gate structure has a top portion defining a portion of the upper corner, and
wherein at least a portion of the top portion is closer to the s

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dohee
• Kim Gyeom
• Kim Jinbum
• Yu Haejun
• Choi Kyungin
• Hwang Kihyun
• Lee Seunghun

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title