Dual liner silicide

Patent metadata

Field	Value
Publication number	US-10395995-B2
Application number	US-201815956082-A
Country	US
Kind code	B2
Filing date	Apr 18, 2018
Priority date	Jun 16, 2015
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

First claim

The invention claimed is:

1. A dual silicide complementary metal oxide semiconductor (CMOS) device comprising:
a P-type device including source and drain regions on opposite sides of a first gate structure and being disposed over a substrate, the source and drain regions including a horizontal portion and a vertical portion;
a first silicided liner formed over the horizontal portion and the vertical portion of the source and drain regions of the P-type device to provide a first silicided liner having only one bent portion;
an N-type device including source and drain regions on opposite sides of a second gate structure and being disposed over the substrate, the source and drain regions including a horizontal portion and a vertical portion;
a second silicided liner formed only on a portion of the horizontal portion of the source and drain regions of the N-type device adjacent to the second gate structure;
a dielectric layer covering the vertical portion and at least a portion of the horizontal portion of the source and drain regions of the P-type device and the N-type device;
a conformal protection layer covering the vertical portion and at least a portion of the horizontal portion of the source and drain regions of the N-type device, said at least portion of the horizontal portion of the source and drain regions being covered by the conformal protection layer being a remainder of the horizontal portion extending from the second silicided liner to the vertical portion of the source and drain regions;
first contacts connecting to the first silicided liner through the high-k dielectric layer; and
second contacts connecting to the second silicided liner through the high-k dielectric layer and the conformal protection layer.

2. The device as recited in claim 1 , wherein the first silicided liner includes at least one of Ni, Pt or a combination thereof.

3. The device as recited in claim 1 , wherein the second silicided liner includes Ti.

4. The device as recited in claim 1 , wherein the vertical surface of the P-type device faces the vertical surface of the N-type device between the devices such that the vertical surfaces are separated by at least two thicknesses of the high-k dielectric layer and the conformal protection layer.

5. The device as recited in claim 1 , wherein the dielectric layer is comprised of a high-k dielectric.

6. The device as recited in claim 1 , wherein the high-k dielectric is HfO 2 .

7. The device as recited in claim 1 , wherein the conformal protection layer includes a nitride containing dielectric.

8. The device as recited in claim 7 , wherein the nitride containing dielectric is silicon nitride.

9. A complementary metal oxide semiconductor (CMOS) device comprising:
a P-type device including source and drain regions including a horizontal portion and a vertical portion;
a first silicided liner formed over the horizontal portion and the vertical portion of the source and drain regions of the P-type device, the first silicided liner having only one bent portion;
an N-type device including source and drain regions including a horizontal portion and a vertical portion;
a second silicided liner formed on a portion of the horizontal portion of the source and drain regions of the N-type device that is adjacent to a gate structure for the N-type device;
a dielectric layer covering the vertical portion and at least a portion of the horizontal portion of the source and drain regions of the P-type device and the N-type device; and
a conformal protection layer covering the vertical portion and at least a portion of the horizontal portion of the source and drain regions of the N-type device, the conformal protection layer covering a remainder of the upper surface of the N-type device that is not covered with the second silicided liner.

10. The device as recited in claim 9 , wherein the first silicided liner includes at least one of Ni, Pt or a combination thereof.

11. The device as recited in claim 9 , wherein the second silicided liner includes Ti.

12. The device as recited in claim 9 , wherein the vertical surface of the P-type device faces the vertical surface of the N-type device between the devices such that the vertical surfaces are separated by at least two thicknesses of the high-k dielectric layer and the conformal protection layer.

13. The device as recited in claim 9 , wherein the high-k dielectric layer includes HfO 2 .

14. The device as recited in claim 9 , wherein the conformal protection layer includes SiN.

15. A complementary metal oxide semiconductor (CMOS) device comprising:
a P-type device including source and drain regions including a horizontal portion and a vertical portion;
a first silicided liner including a metal selected from the group of nickel, platinum and a combination thereof formed over the horizontal portion and the vertical portion of the source and drain regions of the P-type device, the first silicided liner having only one bent portion;
an N-type device including source and drain regions including a horizontal portion and a vertical portion;
a second silicided liner comprising titanium formed on a portion of the horizontal portion of the source and drain regions of the N-type device that is adjacent to a gate structure for the N-type device;
a protection layer covering the vertical portion and at least a portion of the horizontal portion of the source and drain regions of the N-type device, the protection layer covering a remainder of the upper surface of the N-type device that is not covered with the second silicided liner.

16. The device as recited in claim 15 , wherein the first contacts connect to the first silicided liner through the high-k dielectric layer.

17. The device as recited in claim 15 , wherein second contacts connect to the second silicided liner through the high-k dielectric layer and the protection layer.

18. The device as recited in claim 15 , wherein the vertical surface of the P-type device faces the vertical surface of the N-type device between the devices such that the vertical surfaces are separated by at least two thicknesses of the high-k dielectric layer and the conformal protection layer.

19. The device as recited in claim 15 , wherein the first silicided liner includes at least one of Ni, Pt or a combination thereof.

20. The device as recited in claim 15 , wherein the second silicided liner includes Ti.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Pranatharthiharan Balasubramanian
• Xie Ruilong
• Yeh Chun-Chen

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L29/456

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic