Atomic layer deposition of barrier metal layer for electrode of gallium nitride material device

Patent metadata

Field	Value
Publication number	US-12112983-B2
Application number	US-202017003616-A
Country	US
Kind code	B2
Filing date	Aug 26, 2020
Priority date	Aug 26, 2020
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

An electrode structure for a device, such as a GaN or AlGaN device is described. In one example, a method to form the structure includes providing a substrate including gallium nitride material, forming an insulating layer over a surface of the substrate, forming an opening in the insulating layer to expose a surface region of the substrate, depositing a barrier metal layer over the insulating layer and onto the surface region of the substrate through the opening, and depositing a conducting metal layer over the barrier metal layer. In one case, the barrier metal layer includes a layer of tungsten nitride. The layer of tungsten nitride is deposited over the insulating layer and onto the surface region of the substrate using atomic layer deposition.

First claim

Therefore, the following is claimed:

1. A method of manufacturing an electrode structure for a device, comprising:
forming an insulating layer over a surface of a substrate;
forming an opening in the insulating layer to expose a semiconductor material surface region of the substrate through the opening;
depositing a barrier metal layer over the insulating layer and onto the semiconductor material surface region of the substrate through the opening in the insulating layer using atomic layer deposition;
depositing a conducting metal layer over the barrier metal layer;
depositing a cap metal layer over the conducting metal layer using sputtering;
forming a cap etch photoresist layer over a region of the cap metal layer; and
etching the cap metal layer, the conducting metal layer, and the barrier metal layer down to the insulating layer over an area outside of the cap etch photoresist layer.

2. The method according to claim 1 , wherein depositing the barrier metal layer comprises depositing the barrier metal layer onto the insulating layer and onto the semiconductor material surface region of the substrate using atomic layer deposition.

3. The method according to claim 1 , wherein the barrier metal layer comprises tungsten nitride.

4. The method according to claim 1 , wherein depositing the conductive metal layer comprises sputtering the conductive metal layer over the barrier metal layer.

5. The method according to claim 1 , wherein the conducting metal layer comprises aluminum.

6. The method according to claim 1 , wherein the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride.

7. The method according to claim 1 , further comprising removing the cap etch photoresist layer.

8. The method according to claim 1 , wherein:
the substrate comprises a gallium nitride material layer;
forming the opening in the insulating layer comprises exposing a surface region of the gallium nitride material layer; and
depositing the barrier metal layer comprises depositing the barrier metal layer onto the surface region of the gallium nitride material layer.

9. A method of manufacturing an electrode structure for a device, comprising:
providing a substrate comprising a gallium nitride material layer;
forming an insulating layer over a surface of the gallium nitride material layer;
forming an opening in the insulating layer to expose a surface region of the gallium nitride material layer through the opening;
depositing a barrier metal layer over the insulating layer and onto the surface region of the gallium nitride material layer through the opening in the insulating layer using atomic layer deposition;
depositing a conducting metal layer over the barrier metal layer; and
depositing a cap metal layer of at least one of titanium nitride, tungsten, and tungsten nitride over the conducting metal layer using sputtering.

10. The method according to claim 9 , wherein the barrier metal layer comprises tungsten nitride.

11. The method according to claim 9 , wherein depositing the conductive metal layer comprises sputtering the conductive metal layer over the barrier metal layer.

12. The method according to claim 9 , wherein the conducting metal layer comprises aluminum.

13. A method of manufacturing an electrode structure for a device, comprising:
forming an opening in an insulating layer to expose a semiconductor material surface region of a substrate through the opening;
depositing a barrier metal layer over the insulating layer and onto the semiconductor material surface region of the substrate through the opening using atomic layer deposition;
depositing a conducting metal layer over the barrier metal layer using sputtering;
depositing a cap metal layer over the conducting metal layer using sputtering; and
etching the cap metal layer, the conducting metal layer, and the barrier metal layer down to the insulating layer over an area.

14. The method according to claim 13 , wherein:
the substrate comprises a gallium nitride material layer;
forming the opening in the insulating layer comprises exposing a surface region of the gallium nitride material layer; and
depositing the barrier metal layer comprises depositing the barrier metal layer onto the surface region of the gallium nitride material layer.

15. The method according to claim 13 , wherein the conducting metal layer comprises aluminum.

16. The method according to claim 13 , wherein the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride.

17. The method according to claim 13 , wherein the barrier metal layer comprises tungsten nitride.

18. The method according to claim 13 , wherein:
the barrier metal layer comprises tungsten nitride;
the conducting metal layer comprises aluminum; and
the cap metal layer comprises at least one of titanium nitride, tungsten, and tungsten nitride.

19. The method according to claim 13 , wherein depositing the barrier metal layer comprises depositing the barrier metal layer onto the insulating layer and onto the semiconductor material surface region of the substrate using atomic layer deposition.

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Boles Timothy E
• Struble Wayne Mack
• Cueva Gabriel R

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/032 Primary

  of conductive barrier, adhesion or liner layers · CPC title

• H10D30/471

  High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] · CPC title

• H10D30/6738 Primary

  Schottky barrier electrodes · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title