Selective deposition of metal barrier in damascene processes

Patent metadata

Field	Value
Publication number	US-11398406-B2
Application number	US-201816213622-A
Country	US
Kind code	B2
Filing date	Dec 7, 2018
Priority date	Sep 28, 2018
Publication date	Jul 26, 2022
Grant date	Jul 26, 2022

Abstract

A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

First claim

What is claimed is:

1. A method of forming an integrated circuit structure, the method comprising:
forming an etch stop layer over a conductive feature;
forming a dielectric layer over the etch stop layer;
forming an opening in the dielectric layer to reveal the etch stop layer;
etching the etch stop layer through the opening using an etchant comprising an inhibitor, wherein an inhibitor film comprising the inhibitor is formed on the conductive feature;
depositing a conductive barrier layer extending into the opening, wherein the conductive barrier layer forms isolated islands on the inhibitor film;
after the conductive barrier layer is deposited, performing a treatment to remove the inhibitor film, wherein after the treatment, the isolated islands are attached to the conductive features; and
depositing a conductive material to fill a remaining portion of the opening.

2. The method of claim 1 further comprising, after the etch stop layer is etched, soaking a respective wafer comprising the etch stop layer and the inhibitor film in a chemical solution to increase a thickness of the inhibitor film, wherein during the soaking, the etch stop layer is not etched.

3. The method of claim 2 , wherein the etchant and the chemical solution comprises a same type of inhibitor.

4. The method of claim 1 , wherein the etching the etch stop layer is performed using a wet etching chemical comprising the inhibitor, and the inhibitor in the wet etching chemical is attached to the conductive feature to form the inhibitor film.

5. The method of claim 1 , wherein the inhibitor comprises bis-triazolyl indoleamine.

6. The method of claim 1 , wherein the inhibitor in the etchant comprises Benzotriazole, and the conductive feature comprises copper, and wherein the inhibitor film starts to be formed after the etch stop layer is etched-through, and when the Benzotriazole is in contact with the conductive feature.

7. The method of claim 1 , wherein a maximum height of the isolated islands is smaller than a thickness of a sidewall portion of the conductive barrier layer, with the sidewall portion being on a sidewall of the dielectric layer.

8. The method of claim 1 , wherein the isolated islands of the conductive barrier layer are laterally physically spaced apart from both of the dielectric layer and the etch stop layer.

9. The method of claim 8 , wherein the isolated islands are separated from each other by the conductive material.

10. A method of forming an integrated circuit structure, the method comprising:
forming an etch stop layer over a conductive feature;
forming a dielectric layer over the etch stop layer;
forming an opening in the dielectric layer to reveal the etch stop layer;
etching the etch stop layer; and
selectively depositing a conductive barrier layer extending into the opening, wherein the selectively depositing results in the conductive barrier layer to comprise:
first portions directly at a bottom of the opening; and
second portions on sidewalls of the dielectric layer, wherein a maximum thickness of the first portions of the conductive barrier layer is smaller than thicknesses of the second portions of the conductive barrier layer, and wherein an entirety of the first portions and an entirety of the second portions are formed in a same deposition process, and are formed of a same homogenous material.

11. The method of claim 10 , wherein the conductive barrier layer comprises discrete islands at the bottom of the opening, wherein the discrete islands are formed during the selectively depositing, and the discrete islands grow with proceeding of the selectively depositing, and wherein at a time the selectively depositing is finished, the first portions are in the form of the discrete islands.

12. The method of claim 11 , wherein the etching the etch stop layer results in an inhibitor film to be formed on a top surface of the conductive feature, and the conductive barrier layer comprises isolated islands directly over the inhibitor film, and the method further comprises:
after the conductive barrier layer is formed, removing the inhibitor film, wherein after the inhibitor film is removed, the isolated islands are attached to the conductive feature; and
depositing a conductive material to fill a remaining portion of the opening.

13. The method of claim 12 , wherein the removing the inhibitor film comprises a plasma treatment using hydrogen (H 2 ) as a process gas.

14. The method of claim 12 , wherein the inhibitor film comprises bis-triazolyl indoleamine.

15. The method of claim 10 , wherein the conductive barrier layer does not extend to the bottom of the opening.

16. A method of forming an integrated circuit structure, the method comprising:
forming an etch stop layer over a conductive feature;
forming a dielectric layer over the etch stop layer;
etching the dielectric layer to form an opening in the dielectric layer, wherein the etching stops on the etch stop layer;
performing a wet etching process to etch the etch stop layer and to reveal the conductive feature, wherein in the wet etching process, an etching solution is used, and an inhibitor in the etching solution forms an inhibitor film contacting a top surface of the conductive feature, wherein the inhibitor comprises bis-triazolyl indoleamine;
depositing a conductive barrier layer extending into the opening and lining sidewalls of the dielectric layer, wherein the conductive barrier layer comprises:
first portions at a bottom of the opening; and
second portions on sidewalls of the dielectric layer, wherein the first portions start to grow at a time later than a starting time the second portions start to grow; and

after the conductive barrier layer is deposited, depositing a conductive material to fill the opening.

17. The method of claim 16 , wherein the conductive barrier layer forms isolated islands on the inhibitor film, and the method further comprises:
removing the inhibitor film, and after the inhibitor film is removed, the isolated islands are attached to the conductive feature further.

18. The method of claim 16 , wherein the first portions are thinner than the second portions of the conductive barrier layer.

19. The method of claim 16 , wherein the inhibitor film covers a portion of the top surface of the conductive feature, wherein the portion of the top surface is exposed to the opening.

20. The method of claim 16 further comprising:
depositing an etch stop layer over the conductive feature, wherein the dielectric layer is formed over the etch stop layer, and the forming the opening further comprises etching-through the etch stop layer, and wherein the inhibitor film is formed during the etching-through the etch stop layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Chia-Pang
• Lee Ya-Lien
• Shen Chieh-Yi

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/086

  involving buried masks · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/041

  the barrier, adhesion or liner layers being discontinuous · CPC title