Method to compute timing yield and yield bottleneck using correlated sample generation and efficient statistical simulation

Patent metadata

Field	Value
Publication number	US-12112108-B2
Application number	US-202017433595-A
Country	US
Kind code	B2
Filing date	Feb 26, 2020
Priority date	Feb 26, 2019
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.

First claim

The invention claimed is:

1. A method for computing timing yield for an integrated circuit (IC) having a plurality of timing arcs and endpoints, a plurality of subsets of the timing arcs, each subset associated with an endpoint, the method comprising:
a) generating a speed index associated with each timing arc of a first IC sample to determine a random delay value, wherein the same speed index is used for common timing arcs to determine the random delay values for different signal paths through the common timing arcs of an element of the integrated circuit;
b) generating a first delay sample for each timing arc of the first IC sample based on the associated speed index, a delay distribution of the timing arc and a path context;
c) determining a slack for each endpoint of the first IC sample;
d) determining the worst slack from among the slacks determined for the first IC sample;
e) repeating a) through d) for a plurality of IC samples; and
f) determining timing yield for the IC based on the ratio of the number of determined worst slacks that have a non-negative value with respect to the total number of IC samples.

2. The method of claim 1 , wherein the delay distribution for each timing arc is determined based on a variation aware timing analysis.

3. The method of claim 1 , wherein the subset of timing arcs comprises a signal path through a simulated cell.

4. The method of claim 3 , wherein the common timing arcs comprise a timing arc on a first signal path and a second signal path, wherein the delay of the timing arc on the first signal path is different from the delay of the timing arc on the second signal path.

5. The method of claim 4 , further comprising generating a delay matrix having elements that include the delay samples for all timing arcs, each delay matrix representing a simulated sample cell.

6. The method of claim 1 , wherein the speed indexes are generated by a Monte Carlo value generator.

7. The method of claim 1 , wherein determining the slack for each subset of timing arcs includes summing the delay samples for each timing arc of the subset.

8. A computer system comprising:
a) a storage subsystem including an Electronic Design Automation (EDA) module;
b) a processor coupled to the storage subsystem for receiving from the storage subsystem instructions to direct the processor to:
i. generate a speed index associated with timing arc of a first IC sample to determine a random delay value, wherein the same speed index is used for common timing arcs to determine different random delay values for different signal paths through the common timing arcs of an element of the integrated circuit;
ii. generate a first delay sample for each timing arc of the first IC sample based on the associated speed index, a delay distribution of the timing arc and a path context;
iii. determine a slack for each endpoint of the first IC sample;
iv. determine the worst slack from among the slacks determined for the first IC sample;
v. repeat i. through iv. for a plurality of IC samples; and
vi. determine timing yield for the IC based on the ratio of the number of determined worst slacks that have a non-negative value with respect to the total number of IC samples.

9. The computer system of claim 8 , wherein the instructions received from the storage subsystem direct the processor to identify those paths of a particular cell that have a negative slack in the largest number of samples of the particular cell and adjust the design of the particular cell to reduce the likelihood of a negative slack in the identified paths.

10. The computer system of claim 8 , wherein the instructions received from the storage subsystem direct the processor to:
a) generating a delay matrix for the plurality of IC samples;
b) determining the design slack for each of the plurality of IC samples and a design slack distribution for the plurality of IC samples;
c) determining a delay distribution for a first timing arc over the plurality of IC samples;
d) computing a value of a cross moment of:
i. the design slack distribution; with
ii. the delay distribution of delays for the first timing arc; and

e) repeating c) and d) for each timing arc of the IC; and
f) determining in which cells the timing arc results in the cross moment having a value above a predetermined threshold and determining those cells to be timing bottlenecks.

Assignees

• Synopsys Inc

Inventors

• Le Jiayong
• Chai Wenwen
• Ding Li

Classifications

• G06F30/337

  Design optimisation · CPC title

• G06F2119/22

  Yield analysis or yield optimisation · CPC title

• G06F2111/08

  Probabilistic or stochastic CAD · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title