Adaptive tuning of memory device clock rates based on dynamic parameters

Patent metadata

Field	Value
Publication number	US-12112048-B2
Application number	US-202217939186-A
Country	US
Kind code	B2
Filing date	Sep 7, 2022
Priority date	Sep 7, 2022
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determined using multiple parameters. The tuning may be based on system parameters to allow the system to withstand challenges that arise during the operation. The clock frequency table is maintained in the device controller. The table holds the clock frequency of each component. The disclosure proposes modifying the table according to different system environment parameters to maintain performance or reduce power consumption. Adaptive tuning allows a more flexible system design that can adapt according to the current system status. Adaptive tuning also reduces peak power consumption, improves performance, and better quality of service (QoS) compatibility characteristics.

First claim

What is claimed is:

1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller includes an adaptive frequency table that has different clock rates for different data storage device elements as a function of bit error rate (BER), wherein the controller is configured to:
assess system parameters;
determine that BER has changed;
select clock frequency operating parameters from the adaptive frequency table based upon the changed BER; and
update clock frequency of at least one controller component based upon the selected clock frequency.

2. The data storage device of claim 1 , wherein the system parameters are parameters of the memory device.

3. The data storage device of claim 1 , wherein the controller comprises an error correction module, volatile memory, a host interface module (HIM), a flash interface module (FIM), at least one processor, and a frequency monitor (FM).

4. The data storage device of claim 3 , wherein the assessing comprises assessing parameters of one or more of the volatile memory, HIM, FIM, at least one processor, and FM.

5. The data storage device of claim 3 , wherein updating the clock frequency comprises changing the clock frequency of the HIM.

6. The data storage device of claim 5 , wherein updating the clock frequency comprises updating the clock frequency of the at least one processor.

7. The data storage device of claim 3 , wherein updating the clock frequency comprises not updating the clock frequency of the error correction module.

8. The data storage device of claim 1 , wherein the assessing occurs in response to receiving an interrupt signal from a timer.

9. The data storage device of claim 1 , wherein the assessing comprises determining the BER.

10. The data storage device of claim 1 , wherein the assessing comprises determining how many program-erase cycles (PECs) have occurred.

11. The data storage device of claim 1 , wherein the assessing comprises measuring a temperature of the memory device.

12. The data storage device of claim 1 , wherein the updating occurs dynamically.

13. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller includes an adaptive frequency table that has different clock rates for different data storage device elements as a function of bit error rate (BER), wherein the controller is configured to:
detect the BER has exceeded a predetermined threshold; and
dynamically change a clock frequency of one or more of a processor of the controller, a host interface module (HIM) of the controller, a flash interface module (FIM) of the controller, or volatile memory of the controller, wherein the clock frequency is changed to a value from the adaptive frequency table correlating to the detected BER.

14. The data storage device of claim 13 , wherein the controller comprises an error correction module, and wherein the dynamically changing does not change a clock frequency of the error correction module.

15. The data storage device of claim 13 , wherein the dynamically changing comprises changing a clock frequency for a component that is a bottleneck impacting the detected one or more.

16. The data storage device of claim 13 , wherein changing the clock frequency comprises raising the clock frequency or at least one of the processor, the HIM, the FIM, or the volatile memory.

17. The data storage device of claim 16 , wherein changing the clock frequency comprises lowering the clock frequency of at least one of the processor, the HIM, the FIM, or the volatile memory.

18. A data storage device, comprising:
memory means; and
a controller coupled to the memory means, wherein the controller includes an adaptive frequency table that has different clock rates for different data storage device elements as a function of bit error rate (BER), wherein the controller is configured to:
detect the BER has exceeded a predetermined threshold; and
dynamically change a clock frequency of a processor of the controller and a host interface module (HIM) of the controller, wherein the clock frequency is changed to a value from the adaptive frequency table correlating to the detected BER.

19. The data storage device of claim 18 , wherein the controller comprises a system environment analysis module.

Assignees

• Western Digital Tech Inc
• Sandisk Technologies Inc

Inventors

• Benisty Shay
• Navon Ariel
• Bazarsky Alexander
• Avraham David

Classifications

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0625 Primary

  Power saving in storage systems · CPC title

• G06F3/06 Primary

  Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers} · CPC title