Memory device and erasing and verification method thereof

Patent metadata

Field	Value
Publication number	US-12100456-B2
Application number	US-202318141207-A
Country	US
Kind code	B2
Filing date	Apr 28, 2023
Priority date	Apr 28, 2020
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, and a bottom select gate. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the memory string, apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string, and apply a first turn-on voltage to the bottom select gate, before applying the verifying voltage to the at least one word line.

First claim

What is claimed is:

1. A memory device, comprising:
a memory string comprising a top select gate, word lines, and a bottom select gate; and
a control circuit coupled to the memory string and configured to, in an erasing operation:
apply an erasing voltage to the memory string;
apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string;
apply a first turn-on voltage to the bottom select gate before applying the verifying voltage to the at least one word line; and
apply a second turn-on voltage to the top select gate after stopping application of the erasing voltage for a period of time.

2. The memory device of claim 1 , wherein
the memory string further comprises a P-well; and
the control circuit is further configured to apply the erasing voltage to the P-well.

3. The memory device of claim 1 , wherein the control circuit is further configured to:
apply the first turn-on voltage to the bottom select gate, maintaining at least until applying the second turn-on voltage to the top select gate.

4. The memory device of claim 1 , wherein the control circuit is further configured to:
apply the first turn-on voltage to the bottom select gate, maintaining at least until applying the verifying voltage to the at least one word line.

5. The memory device of claim 1 , wherein the control circuit is further configured to:
float the bottom select gate before applying the first turn-on voltage to the bottom select gate; and
apply the first turn-on voltage to the bottom select gate, starting after a floating voltage on the bottom select gate drops.

6. The memory device of claim 5 , wherein the control circuit is further configured to:
apply the first turn-on voltage to the bottom select gate, starting when the floating voltage on the bottom select gate drops to the first turn-on voltage.

7. The memory device of claim 5 , wherein the control circuit is further configured to:
apply the first turn-on voltage to the bottom select gate, starting after the floating voltage on the bottom select gate drops to a voltage lower than the first turn-on voltage.

8. The memory device of claim 2 , wherein the control circuit is further configured to apply the first turn-on voltage to the bottom select gate, starting before a voltage on the P-well drops from the erasing voltage to zero.

9. The memory device of claim 1 , wherein the control circuit is further configured to apply a voltage proximity 0V to the at least one word line during applying the erasing voltage to the memory string.

10. The memory device of claim 1 , wherein the control circuit is further configured to apply the first turn-on voltage to the bottom select gate, starting when the erasing voltage is applied to the memory string.

11. A method for operating a memory device comprising a memory string, the memory string comprising a top select gate, word lines, and a bottom select gate, the method comprising:
applying an erasing voltage to the memory string;
applying a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string;
applying a first turn-on voltage to the bottom select gate before applying the verifying voltage to the at least one word line; and
applying a second turn-on voltage to the top select gate after stopping application of the erasing voltage for a period of time.

12. The method of claim 11 , wherein the memory string further comprises a P-well; and
applying the erasing voltage to the memory string comprising: applying the erasing voltage to the P-well.

13. The method of claim 11 , further comprising:
applying the first turn-on voltage to the bottom select gate, maintaining at least until applying the second turn-on voltage to the top select gate.

14. The method of claim 11 , further comprising:
applying the first turn-on voltage to the bottom select gate, maintaining at least until applying the verifying voltage to the at least one word line.

15. The method of claim 11 , further comprising:
floating the bottom select gate before applying the first turn-on voltage to the bottom select gate; and
applying the first turn-on voltage to the bottom select gate, starting after a floating voltage on the bottom select gate drops.

16. The method of claim 15 , wherein applying the first turn-on voltage to the bottom select gate, starting when the floating voltage on the bottom select gate drops to the first turn-on voltage.

17. The method of claim 15 , wherein applying the first turn-on voltage to the bottom select gate, starting after the floating voltage on the bottom select gate drops to a voltage lower than the first turn-on voltage.

18. The method of claim 12 , wherein further comprising applying the first turn-on voltage to the bottom select gate, starting before a voltage on the P-well drops from the erasing voltage to zero.

19. The method of claim 11 , further comprising applying the first turn-on voltage to the bottom select gate, starting when the erasing voltage is applied to the memory string.

20. A memory system, comprising:
a memory device comprising:
a memory string comprising a top select gate, word lines, and a bottom select gate; and
a control circuit coupled to the memory string and configured to, in an erasing operation:
apply an erasing voltage to the memory string;
apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string;

apply a first turn-on voltage to the bottom select gate before applying the verifying voltage to the at least one word line; and
apply a second turn-on voltage to the top select gate after stopping application of the erasing voltage for a period of time.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Li Kaiwei
• Jia Jianquan
• Liu Hongtao
• Zhang An

Classifications

• G11C16/3445 Primary

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C2211/5621

  Multilevel programming verification · CPC title

• G11C11/5635

  Erasing circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title