Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2016240264-A1
Application number	US-201615046231-A
Country	US
Kind code	A1
Filing date	Feb 17, 2016
Priority date	Feb 18, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

A semiconductor memory device includes a first memory cell, a first word line electrically connected to a gate of the first memory cell, a first bit line electrically connected to one end of the first memory cell, and a controller configured to execute a write operation, which includes a first cycle and a second cycle that is executed after the first cycle. The first cycle includes a first operation of applying a program voltage to the first word line, a second operation executed after the first operation of applying a first voltage to the first bit line and a second voltage lower than the first voltage to the first word line, and a third operation executed after the second operation of applying a verify voltage to the first word line. The second cycle includes the first operation and then the third operation, and excludes the second operation.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a first memory cell; a first word line electrically connected to a gate of the first memory cell; a first bit line electrically connected to one end of the first memory cell; and a controller configured to execute a write operation, which includes a plurality of cycles including a first cycle and a second cycle that is executed after the first cycle, wherein the first cycle includes a first operation of applying a program voltage to the first word line, a second operation executed after the first operation of applying a first voltage to the first bit line and a second voltage lower than the first voltage to the first word line, and a third operation executed after the second operation of applying a verify voltage to the first word line, and the second cycle includes the first operation and then the third operation, and excludes the second operation.

2 . The device according to claim 1 , further comprising:
a second memory cell having a gate to which the first word line is electrically connected; and a second bit line electrically connected to one end of the second memory cell, wherein the second cycle further includes a fourth operation of applying a third voltage to the second bit line and the second voltage to the first word line, the third voltage being lower than the first voltage, the fourth operation being executed between the first and third operations.

3 . The device according to claim 2 , further comprising:
a third memory cell; and a second word line electrically connected to a gate of the third the memory cell, wherein a pass voltage lower than the program voltage is applied to the second word line in the first operation, a fourth voltage higher than the first voltage is applied to the second word line in the second operation and the fourth operation, and a read voltage higher than the verify voltage is applied to the second word line in the third operation.

4 . The device according to claim 3 , further comprising:
a first select transistor arranged between one end of the first memory cell and the first bit line; a second select transistor arranged between one end of the second memory cell and the second bit line; a fourth memory cell having a gate electrically connected to the first word line; and a third select transistor arranged between one end of the fourth memory cell and the first bit line, wherein in the second operation, a fifth voltage is applied to the gates of the first select transistor and the second select transistor, and a sixth voltage to a gate of the third select transistor.

5 . The device according to claim 4 , wherein
wherein in a state where the fifth voltage is applied to the gates of the first and second select transistors, the first select transistor is in a non-conductive state and a channel potential of the first memory cell and a potential of the first bit line are different, the second select transistor is in a conductive state so that a channel potential of the second memory cell is at the third voltage.

6 . The device according to claim 5 , wherein
at a start of the second operation, a seventh voltage higher than the fifth voltage is applied to the gate of the third select transistor so that the third select transistor is in the conductive state.

7 . The device according to claim 6 , wherein
the seventh voltage is maintained for a period of time to boost a voltage of the first word line, and then, the sixth voltage lower than the seventh voltage is applied to the gate of the third select transistor, so that the third select transistor is in the non-conductive state.

8 . The device according to claim 4 , wherein the sixth voltage is lower than the fifth voltage.

9 . The device according to claim 1 , wherein the second voltage is lower than a source line voltage.

10 . The device according to claim 1 , further comprising:
a row decoder that supplies voltages to the first and second word lines.

11 . A method of executing a write operation in a semiconductor memory device that includes a first memory cell, a first word line electrically connected to a gate of the first memory cell, and a first bit line electrically connected to one end of the first memory cell, said method comprising:
executing the write operation in multiple cycles including a first cycle and a second cycle that is executed after the first cycle, wherein the first cycle includes a first operation of applying a program voltage to the first word line, a second operation executed after the first operation of applying a first voltage to the first bit line and a second voltage lower than the first voltage to the first word line, and a third operation executed after the second operation of applying a verify voltage to the first word line, and the second cycle includes the first operation and then the third operation, and excludes the second operation.

12 . The method according to claim 11 , wherein the semiconductor memory device further includes a second memory cell having a gate to which the first word line is electrically connected, and a second bit line electrically connected to one end of the second memory cell, wherein
the second cycle further includes a fourth operation of applying a third voltage to the second bit line and the second voltage to the first word line, the third voltage being lower than the first voltage, the fourth operation being executed between the first and third operations.

13 . The method according to claim 12 , wherein the semiconductor memory device further includes a third memory cell, and a second word line electrically connected to a gate of the third memory cell, wherein
a pass voltage lower than the program voltage is applied to the second word line in the first operation, a fourth voltage higher than the first voltage is applied to the second word line in the second operation and the fourth operation, and a read voltage higher than the verify voltage is applied to the second word line in the third operation.

14 . The method according to claim 13 , wherein the semiconductor memory device further includes a first select transistor arranged between one end of the first memory cell and the first bit line, a second select transistor arranged between one end of the second memory cell and the second bit line, a fourth memory cell having a gate electrically connected to the first word line, and a third select transistor arranged between one end of the fourth memory cell and the first bit line, wherein
in the second operation, a fifth voltage is applied to the gates of the first select transistor and the second select transistor, and a sixth voltage to a gate of the third select transistor.

15 . The method according to claim 14 , wherein
wherein in a state where the fifth voltage is applied to the gates of the first and second select transistors, the first select transistor is in a non-conductive state and a channel potential of the first memory cell and a potential of the first bit line are different, the second select transistor is in a conductive state so that a channel potential of the second memory cell is at the third voltage.

16 . The method according to claim 15 , wherein
at a start of the second operation, a seventh voltage higher than the fifth voltage is applied to the gate of the third select transistor so that the third select transistor is in the conductive state.

17 . The method according to claim 16 , wherein
the seventh voltage is maintained for a period of time to boost a voltage of the

Assignees

• Toshiba Kk

Inventors

• Hosono Koji

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/3454

  Arrangements for verifying correct programming or for detecting overprogrammed cells · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title