Operation method of a nonvolatile memory device for controlling a resume operation

Patent metadata

Field	Value
Publication number	US-2018151237-A1
Application number	US-201715825786-A
Country	US
Kind code	A1
Filing date	Nov 29, 2017
Priority date	Nov 29, 2016
Publication date	May 31, 2018
Grant date	—

Abstract

An operation method of a nonvolatile memory device for programming memory cells connected to a selected word line, the method including: performing a program operation; suspending the program operation after performing a first portion of the program operation; and resuming the program operation to perform a second portion of the program operation, wherein the program operation is resumed within a reference time after the program operation is suspended.

First claim

1 . An operation method of a nonvolatile memory device for programming memory cells connected to a selected word line, the method comprising:
performing a program operation; suspending the program operation after performing a first portion of the program operation; and resuming the program operation to perform a second portion of the program operation, wherein the program operation is resumed within a reference time after the program operation is suspended.

2 . The operation method of claim 1 , wherein the reference time is a length of time for securing reliability of the program operation with respect to a threshold voltage distribution of the suspended program operation.

3 . An operation method of a nonvolatile memory device for erasing a selected memory block from among a plurality of memory blocks, the method comprising:
performing an erase operation; suspending the erase operation after performing a first portion of the erase operation; and resuming the erase operation to perform a second portion of the erase operation, wherein the erase operation is resumed within a reference time after the erase operation is suspended.

4 . The operation method of claim 3 , wherein the reference time is a length of time for securing reliability of the erase operation with respect to a threshold voltage distribution of the suspended erase operation.

5 . An operation method of a nonvolatile memory device for programming memory cells connected to a selected word line by sequentially performing a plurality of program loops, the method comprising:
performing a first portion of a program operation, wherein the program operation comprises at least one of the plurality of program loops; suspending the program operation after the performing of the first portion of the program operation; and resuming the program operation after the suspending of the program operation, wherein the program operation is resumed for the selected word line or a word line different than the selected word line, according to a resume time from after the program operation is suspended until the program operation resumes.

6 . The operation method of claim 5 , wherein the suspending of the program operation after the performing of the first portion of the program operation comprises:
suspending the program operation in response to a retrieve request received by the nonvolatile memory device; and performing a read operation of the nonvolatile memory device.

7 . The operation method of claim 5 , wherein the resuming of the program operation after the suspending of the program operation comprises:
determining whether the resume time has elapsed as much as a reference time, wherein the reference time is a length of time for securing program operation reliability of a threshold voltage distribution of the first portion of the program operation.

8 . The operation method of claim 7 , wherein the resuming of the program operation after the suspending of the program operation comprises:
when the resume time is not greater than the reference time, performing, after the first portion of the program operation, a second portion of the program operation comprising the remainder of the plurality of program loops.

9 . The operation method of claim 8 , wherein the resuming of the program operation after the suspending of the program operation comprises:
when the resume time is equal to or greater than the reference time, ignoring the first portion of the program operation, and programming memory cells connected to the different word line.

10 . The operation method of claim 7 , wherein the resuming of the program operation after the suspending of the program operation comprises:
when the resume time is equal to or greater than the reference time, performing, after the first portion of the program operation, a second portion of the program operation comprising the remainder of the plurality of program loops; and after completing the program operation of the selected word line, programming memory cells connected to the different word line.

11 . The operation method of claim 7 , wherein the resuming of the program operation after the suspending of the program operation comprises:
when the resume time is equal to or greater than the reference time, performing, after the first portion of the program operation, a second portion of the program operation comprising the remainder of the plurality of program loops; detecting and correcting an error for data that is programmed to the memory cells of the selected word line; and programming memory cells connected to the different word line.

12 .- 15 . (canceled)

16 . An operation method of a nonvolatile memory device for erasing a selected memory block from among a plurality of memory blocks by sequentially performing a plurality of erase loops, the method comprising:
performing a first portion of an erase operation, wherein the erase operation comprises at least one of the plurality of erase loops; suspending the erase operation after the performing of the first portion of the erase operation; and resuming the erase operation after the suspending of the erase operation, wherein the remainder of the plurality of erase loops are performed according to a resume time from after the erase operation is suspended until the erase operation resumes, or all of the plurality of erase loops are performed again from the beginning of the sequence.

17 . The operation method of claim 16 , wherein the suspending of the erase operation after the performing of the first portion of the erase operation comprises:
suspending the erase operation in response to a retrieve request received by the nonvolatile memory device; and performing a read operation of the nonvolatile memory device.

18 . The operation method of claim 16 , wherein the resuming of the erase operation after the suspending of the erase operation comprises:
determining whether the resume time has elapsed as much as a reference time, wherein the reference time is a length of time for securing reliability of the erase operation with respect to a threshold voltage distribution of the first portion of the erase operation.

19 . The operation method of claim 18 , wherein the resuming of the erase operation after the suspending of the erase operation further comprises:
when the resume time is not greater than the reference time, performing, after the first portion of the erase operation, a second portion of the erase operation comprising the remainder of the plurality of erase loops.

20 . The operation method of claim 18 , wherein the resuming of the erase operation after the suspending of the erase operation further comprises:
when the resume time is equal to or greater than the reference time, performing a pre-program operation on the selected memory block; and performing the plurality of erase loops again starting from the beginning of the sequence on the selected memory block.

21 . The operation method of claim 20 , wherein, when the resume time is equal to or greater than the reference time, the performing of the pre-program operation on the selected memory block comprises:
applying a program voltage to a plurality of word lines connected to the selected memory block.

22 . The operation method of claim 18 , wherein the resuming of the erase operation after the suspending of the erase operation further comprises:
when the resume time is equal to or greater than the reference time, ignoring the first portion of the erase operation, and erasing a memory bl

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Ji-Sang
• Cho Ji-Ho
• Kim Byung-Soo
• Shin Dong-Jin

Classifications

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title