Recovery of partially programmed block in non-volatile memory

Patent metadata

Field	Value
Publication number	US-9460799-B1
Application number	US-201514951347-A
Country	US
Kind code	B1
Filing date	Nov 24, 2015
Priority date	Nov 24, 2015
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

Techniques for recovery of partially programmed blocks in non-volatile storage are disclosed. After programming memory cells in an open region of a partially programmed block, a fail bit count with respect to programming the memory cells is performed. If the fail bit count is above a threshold, then a recovery operation is performed of other memory cells in the partially programmed block. The recovery operation (such as erase) may remove charges that are trapped in the tunnel dielectric of memory cells in the open region of the partially programmed block. Note that this erase operation may be performed on memory cells in the open region that are already erased. The erase operation may remove trapped charges from the tunnel dielectric. In a sense, this “resets” the memory cells. Thus, the memory cells can now be programmed more effectively. Both programming and date retention may be improved.

First claim

What is claimed is:

1. A non-volatile storage device, comprising:
a plurality of blocks that comprise non-volatile storage elements; and
managing circuitry in communication with the non-volatile storage elements; the managing circuitry configured to program a set of non-volatile storage elements in a block that comprises programmed non-volatile storage elements and unprogrammed non-volatile storage elements; the managing circuitry configured to determine a fail bit count of programming the set of non-volatile storage elements; the managing circuitry configured to perform a recovery operation that involves unprogrammed non-volatile storage elements in the block other than those in the set, in response to determining that the fail bit count exceeds a first threshold, to perform the recovery operation the managing circuitry configured to program one or more of the unprogrammed non-volatile storage elements in the block with dummy data when the fail bit count is less than a second threshold.

2. The non-volatile storage device of claim 1 , wherein to perform the recovery operation the managing circuitry is further configured to save data from the programmed non-volatile storage elements in the block to another location, and erase the programmed and the unprogrammed non-volatile storage elements in the block when the fail bit count is greater than the second threshold.

3. The non-volatile storage device of claim 2 , wherein to perform the recovery operation the managing circuitry is further configured to write a dummy pattern to the programmed and the unprogrammed non-volatile storage elements in the block after erasing the block.

4. The non-volatile storage device of claim 1 , wherein to perform the recovery operation the managing circuitry is further configured to:
erase the block multiple times and write a different dummy pattern to the block after each erase when the fail bit count is greater than a third threshold that is higher than the second threshold.

5. The non-volatile storage device of claim 4 , wherein the managing circuitry is further configured to:
wait a data retention time after writing a last of the dummy patterns to the block;
determine a fail bit count with respect to writing the last dummy pattern to the block after waiting the data retention time; and
retire the block in response to the fail bit count with respect to writing the last dummy pattern being greater than a data retention fail bit threshold.

6. The non-volatile storage device of claim 1 , wherein to perform the recovery operation the managing circuitry is configured to apply an erase operation to the unprogrammed non-volatile storage elements in the block while leaving programmed non-volatile storage elements in the block programmed when the fail bit count is greater than the second threshold.

7. The non-volatile storage device of claim 1 , further comprising a three-dimensional memory array, wherein the non-volatile storage elements reside within the three-dimensional memory array.

8. The non-volatile storage device of claim 1 , further comprising:
a plurality of word lines, wherein each of the non-volatile storage elements is associated with a word line of the plurality of word lines, wherein to program the set of the non-volatile storage elements in the block the managing circuitry is configured to program non-volatile storage elements associated with a first word line of the plurality of word lines, wherein to perform the recovery operation the managing circuitry is configured to perform an erase operation for non-volatile storage elements associated with a second word line for which the non-volatile storage elements are already erased when the fail bit count is greater than the second threshold.

9. A method, comprising:
receiving a programming request;
programming a selected unprogrammed word line in a partially programmed block in response to the programming request, wherein the partially programmed block has a programmed region with one or more word lines programmed and an unprogrammed region with the selected unprogrammed word line and one or more other unprogrammed word lines;
determining a fail bit count of programming the selected first unprogrammed word line; and
performing a recovery operation with respect to the unprogrammed region in the partially programmed block, in response to determining that the fail bit count exceeds a threshold, comprising performing an erase operation of at least the one or more other unprogrammed word lines in the unprogrammed region.

10. The method of claim 9 , wherein performing the recovery operation further comprises:
saving data from the programmed region of the partially programmed block to another location;
erasing the partially programmed block;
writing a dummy pattern to the partially programmed block after erasing the partially programmed block; and
marking the partially programmed block as an open block after writing the dummy pattern.

11. The method of claim 9 , wherein the threshold is a first threshold, wherein performing the recovery operation comprises:
performing a less aggressive erase if the fail bit count is greater than or equal to the first threshold but less than a second threshold; and
performing a more aggressive erase if the fail bit count is greater than or equal to the second threshold.

12. The method of claim 11 , wherein the less aggressive erase comprises erasing the partially programmed block a single time, wherein the more aggressive erase comprises erasing the partially programmed block multiple times.

13. The method of claim 9 , further comprising:
waiting a data retention time after writing a dummy pattern to the partially programmed block;
determining a fail bit count with respect to writing the last dummy pattern to the partially programmed block after waiting the data retention time;
retiring the partially programmed block in response to the fail bit count with respect to writing the dummy pattern being greater than or equal to a data retention fail bit threshold; and
marking the partially programmed block as ready for a new operation in response to the fail bit count with respect to writing the dummy pattern being less than the data retention fail bit threshold.

14. The method of claim 9 , wherein performing the recovery operation comprises:
erasing the partially programmed block;
writing a dummy pattern to the partially programmed block;
waiting a data retention time after writing the dummy pattern to the partially programmed block;
determining a fail bit count with respect to writing the dummy pattern to the partially programmed block after waiting the data retention time; and
erasing the partially programmed block again in response to the fail bit count with respect to writing the dummy pattern being greater than or equal to a data retention fail bit threshold.

15. The method of claim 9 , wherein performing the recovering operation comprises:
erasing only the one or more other unprogrammed word lines in the unprogrammed region of the partially programmed block.

16. A non-volatile storage device, comprising:
a plurality of word lines;
a plurality of NAND strings of non-volatile storage elements arranged in blocks, wherein each of the NAND strings is associated with the plurality of word lines; and
managing circuitry in communication with the plurality of word lines and with the plurality of NAND strings, wherein the managing circuitry selects a partially programmed block of the non-volatile storage elements to program, wherein the partially programmed block comprises programmed word lines and unprogram

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Costa Xiying
• Lee Dana
• Zhou Zhenming

Classifications

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title